參數(shù)資料
型號: HSP50016
廠商: Intersil Corporation
英文描述: Digital Down Converter(數(shù)字式下變頻轉(zhuǎn)換器)
中文描述: 數(shù)字下變頻器(數(shù)字式下變頻轉(zhuǎn)換器)
文件頁數(shù): 15/30頁
文件大?。?/td> 258K
代理商: HSP50016
3-15
TABLE 5. PHASE GENERATOR REGISTER
DESTINATION ADDRESS = 2
BIT
POSITION
FUNCTION
DESCRIPTION
39-37
Address
010 = Control Word 2
36
Update
0 = Update Only This Control Register
1 = Update All Control Registers
35-32
Reserved
All Zeroes
31-0
Maximum Phase
Increment
Bits 31-0 = 2
31
... 2
0
. Range: is 0
<
Maximum Phase Increment <
π
(1-2
-32
) radians.
This parameter is only used in the CHIRP modes, and this is the largest allowable phase increment. Set
to 0 in the Filter Only and CW modes.
TABLE 6. PHASE GENERATOR/OUTPUT TIME SLOT REGISTER
DESTINATION ADDRESS = 3
BIT
POSITION
FUNCTION
DESCRIPTION
39-37
Address
011 = Control Word 3
36
Update
0 = Update Only This Control Register
1 = Update All Control Registers
35-32
Reserved
All Zeroes
31-18
Time Slot Length
Time Slot Length in IQCLK Periods; Bits 31-18 = 2
13
... 2
0
. Range is (19,25, 33, 37, 39, 49, 65 and 77)
The equation for calculating the value for this field is:
TSL = [[(Number of Output Bits + 2)Mode ] + 1]Hex
;
where mode is 2 if the DDC is in either the real or I followed by Q mode. Mode is 1 for all other DDC
operational modes.
Allowable Minimum Time Slot Lengths:
(18)1 + 1 = 19 (13 hexidecimal)
(18)2 + 1 = 37 (25 hexidecimal); Real Output or I followed by Q
(24)1 + 1 = 25 (19 hexidecimal)
(24)2 + 1 = 49 (31 hexidecimal); Real Output or I followed by Q
(32)1 + 1 = 33 (21 hexidecimal)
(32)2 + 1 = 65 (41 hexidecimal); Real Output or I followed by Q
(38)1 + 1 = 39 (27 hexidecimal)
(38)2 + 1 = 77 (4d hexidecimal); Real Output or I followed by Q
17-0
Phase Offset
Starting Phase Angle of Phase Accumulator; Range = 0 to 2
π
. Bits 17-0 = 2
32
... 2
15
.
Some example phase offset hexidecimal values :
0000
- 0
1000
-
π
/2
2000
-
π
3000
- 3
π
/2
3fff
- 2
π
HSP50016
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