參數(shù)資料
型號(hào)： HSP50016
廠商： Intersil Corporation
英文描述： Digital Down Converter(數(shù)字式下變頻轉(zhuǎn)換器)
中文描述： 數(shù)字下變頻器（數(shù)字式下變頻轉(zhuǎn)換器）
文件頁(yè)數(shù)： 13/30頁(yè)
文件大小： 258K
代理商： HSP50016
3-13
Note that Equation 15 is useful in all modes for calculating
the number of IQCLKs necessary to complete one output
data cycle. For a given decimation rate and output word
length, the maximum value in the IQCLK Rate field is:
where Floor(X) represents the integer part of X, R is the
HDF decimation factor, 4 is the FIR decimation factor.
Example Clock Calculations
Clarification of the use of Equations 14-16, the calculation of
the HDF and FIR clocks and the calculation of the IQCLK is
best done by example:
The sample clock, CLK, is 10MHz . . . . . . . . CLK = 10MHz
The HDF Decimation Factor, R, is 100 (which makes the
decimation counter preload = 99). . . . . . . . . . . . . . . R = 100
The Output Mode is I followed by Q. . . . . . . . . . . . Mode = 2
Complex output . . . . . . . . . . . . . . . . . . . FIR Decimation = 4
The desired number of output bits is 32.
1. We begin by identifying the HDF Input Rate:
HDF Input Rate = CLK = 10MHz . . . . . . . CLK = 10MHz
2. Next we calculate the HDF Output Rate:
HDF Output Rate = CLK/R = 10MHz/(100) = 100kHz
. . . . . . . . . . . . . . . . . . . . . . .HDF Output Rate = 100kHz
3. Next we calculate the FIR output Rate:
FIR Output Rate = CLK/4R = 25kHz.
. . . . . . . . . . . . . . . . . . . . . . . . FIR Output Rate = 25kHz
4. Next we calculate the minimum time slot length:
Equation 15:
Length
MIN
= [(Number of Output Bits + 2) x Mode] +1
where the number of output bits = 32 and the Mode is 2
because of the I followed by Q output selection.
Length
MIN
= [(32 + 2) x 2] +1 = 69 IQCLKs
. . . . . . . . . . . . . . . . . . . . . . . . . Length
MIN
= 69 IQCLKs
5. Next we calculate the IQCLK frequency:
IQCLK frequency = [( F
S
)(Length
MIN
)/(R)(4)] - 1
IQCLK frequency = [(10MHz)(69)/(100)(4)] - 1 = 1.725MHz
The IQCLK frequency can be no slower than 1.725MHz if
all of the bits are to be output of the DDC in a time slot.
. . . . . . . . . . . . .Slowest Serial Output Rate = 1.725MHz
6. The Programmed value for the maximum IQCLK Rate,
from Equation 16, is:
IQCLKRATE
MAX
= Floor[(R) x 4/ Length
MIN
] -1
IQCLKRATE
MAX
= Floor[(100 x 4)/69] - 1 = 4
The IQCLKRATE can be not greater than 4 if all of the bits
are to be output of the DDC in a time slot.
. . . . . . . . . . . Control Word Value for IQCLK Ratemax =
[00004]H; 0 0000 0000 0100
LSB
7. Let’s sanity check with Equation 14.
IQCLK Rate = [(CLK/IQCLKfreq)-1] = [10E6/1.725E6] -1 = 4.
This checks!
Control Word Input
The DDC has eight 40-bit control words which are loaded
through the four pin control interface. The format and timing
of this interface is compatible with the serial interface timing
of most common DSP microprocessors (see Figure 14). The
words are shifted MSB first, where bit 39 of the control word
is the MSB. Bits 39 through 37 are the control word address,
i.e., the target control buffer. CS must go low before bit 35 is
clocked in. All 40 bits of the control word must be loaded.
The formats of the control words are shown in Tables 3
through 10.
The control words are double buffered: each control word is
initially loaded into one of eight control buffers for
subsequent down loading into the corresponding Control
Register. The internal circuitry of the DDC uses the Control
Registers to regulate its operation. Control buffers can be
downloaded in one of two ways. Loading a Buffer Register
with bit 36 = 1 causes all Control Registers to be updated
from their respective control buffers when the current word
is finished loading. If bit 36 = 0, then only that control buffer
is updated and the operation of the DDC is not affected. All
Control Registers are updated from their respective buffers
on the third rising edge of CLK following the deassertion of
RESET.
NOTE: Control Word 0 is unique in that it is
only used to update the seven Control Registers, and it
is recognized by the DDC regardless of the state of CS.
In systems with multiple DDCs, this allows the user to
update the configuration of all chips simultaneously without
using RESET.
To ensure that the control information is properly loaded, the
frequency of CLK must be greater than the frequency of
CCLK. In addition, RESET must remain inactive during the
loading of a control word.
IQCLKRate
MAX
Floor
R
MIN
------------------------------
=
1;
–
(EQ. 16)
HSP50016
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