參數(shù)資料
型號: HMS81C43XX
廠商: Hynix Semiconductor Inc.
英文描述: CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER FOR TELEVISION
中文描述: CMOS單芯片8位單片機電視
文件頁數(shù): 82/100頁
文件大?。?/td> 1943K
代理商: HMS81C43XX
HMS81C43xx / GMS87C4060
82
November 2001 ver 1.2
22. RESET
The HMS81C43xx/GMS87C4060 have two types of reset
generation procedures; one is an external reset input, other
is a watch-dog timer reset. Table 22-1 shows on-chip hard-
ware initialization by reset action.
Table 22-1 Initializing Internal Status by Reset Action
22.1 External Reset Input
The reset input is the RESET pin, which is the input to a
Schmitt Trigger. A reset in accomplished by holding the
RESET pin low for at least 8 oscillator periods, within the
operating voltage range and oscillation stable, a reset is ap-
plied and the internal state is initialized. After reset, 64ms
(at 4 MHz) add with 7 oscillator periods are required to
start execution as shown in Figure 22-2 .
Internal RAM is not affected by reset. When V
DD
is turned
on, the RAM content is indeterminate. Therefore, this
RAM should be initialized before reading or testing it.
When the RESET pin input goes high, the reset operation
is released and the program execution starts at the vector
address stored at addresses FFFE
H
- FFFF
H
.
A connecting for simple power-on-reset is shown in Figure
22-1 .
Figure 22-1 Simple Power-on-Reset Circuit
Figure 22-2 Timing Diagram after RESET
On-chip Hardware
Initial Value
On-chip Hardware
Initial Value
Program counter
PC
(FFFF
H
) - (FFFE
H
)
Peripheral clock
Off
RAM page register
DPGR
00
H
Watchdog timer
Disable
G-flag of PSW
G
0
Control registers
Refer to Table 8-1 on page 22
RESET
+
V
DD
GND
MCU
MAIN PROGRAM
Oscillator
(X
IN
pin)
FFFE FFFF
Stabilization Time
t
ST
= 62.5mS at 4.19MHz
RESET
ADDRESS
BUS
DATA
BUS
1
2
3
4
5
6
7
Start
FE
ADL
ADH
OP
RESET Process Step
~
~
~
~
~
~
t
ST
=
x 256
f
MAIN
÷
1024
1
Fetch
~
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