參數(shù)資料
型號(hào)： HMS81C43XX
廠商： Hynix Semiconductor Inc.
英文描述： CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER FOR TELEVISION
中文描述： CMOS單芯片8位單片機(jī)電視
文件頁(yè)數(shù)： 66/100頁(yè)
文件大小： 1943K
代理商： HMS81C43XX
HMS81C43xx / GMS87C4060
66
November 2001 ver 1.2
Figure 18-6 I
2
C control Register 2
Figure 18-7 Interrupt request signal generation timing
START condition generation
When the ESO bit of the I
2
C control register (00DB
H
) is
“1”, writing to the I
2
C status register will generate START
condition. Refer to Figure 18-8 for the START condition
generation timing diagram.
Figure 18-8 START condition generation timing
RESTART condition generation
RESTART condition’s setting sequence is as followings.
1. Write 020
H
to I
2
C status register (ICSR, 00DA
H
)
2. Write slave address to I
2
C data shift register (ICDR,
00D9
H
)
3. Write 0F0
H
to I
2
C status register (ICSR, 00DA
H
)
STOP condition generation
Writing ‘C0h’ to ICSR will generate a stop condition,
3
2
1
0
CCR3
CCR2
CCR1
CCR0
SCL Frequency selection
SCL frequency = f
ex
/ (12 * CCR)
Value
f
ex
= 12MHz
f
ex
= 8MHz
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Not allowed
Not allowed
500.0KHz
333.3KHz
250.0KHz
200.0KHz
166.6KHz
142.9KHz
125.0KHz
111.1KHz
100.0KHz
90.0KHz
83.3KHz
76.4KHz
71.4KHz
66.6KHz
Not allowed
Not allowed
333.3KHz
222.2KHz
166.6KHz
133.3KHz
111.1KHz
95.2KHz
83.3KHz
74.1KHz
66.6KHz
60.6KHz
55.5KHz
51.3KHz
47.6KHz
44.4KHz
Bit
No.
Name
Function
Table 18-3 Bit function
ICCR2
ADDRESS : 00DC
RESET VALUE : 000- 0000
b
RW
RW
RW
RW
RW
RW
ACLK
ACK
1
CCR3 CCR2
CCR1 CCR0
SCL
PIN
I
2
C Request
ICSR write signal
(I
C status reg.)
SCL
SDA
BB (Bus busy) flag
t
SETUP
t
HOLD
t
BB
: Setup time
: Hold time
: Set time for BB
t
SETUP
t
HOLD
t
BB
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