參數(shù)資料
型號： HMS81C43XX
廠商： Hynix Semiconductor Inc.
英文描述： CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER FOR TELEVISION
中文描述： CMOS單芯片8位單片機電視
文件頁數(shù)： 69/100頁
文件大?。?/td> 1943K
代理商： HMS81C43XX
HMS81C43xx / GMS87C4060
69
November 2001 ver 1.2
19. INTERRUPTS
The HMS81C43xx/GMS87C4060 interrupt circuits con-
sist of Interrupt enable register (IENH, IENL), Interrupt re-
quest flags of IRQH, IRQL, Priority circuit and Master
enable flag ("I" flag of PSW). 16 interrupt sources are pro-
vided. The configuration of interrupt circuit is shown in
Figure 19-2 .
Below table shows the Interrupt priority
The External Interrupts can each be transition-activated (1-
to-0 or 0-to-1 transition).
When an external interrupt is generated, the flag that gen-
erated it is cleared by the hardware when the service rou-
tine is vectored to only if the interrupt was transition-
activated.
The Timer/Counter Interrupts are generated by
TnIF(n=0~3), which is set by a match in their respective
timer/counter register.
The Basic Interval Timer Interrupt is generated by BITIF
which are set by a overflow in the timer register.
The interrupts are controlled by the interrupt master enable
flag I-flag (bit 2 of PSW), the interrupt enable register
(IENH, IENL) and the interrupt request flags (in
IRQH,IRQL) except Power-on reset and software BRK in-
terrupt.
Interrupt Mode Register
It controls interrupt priority. It takes only one specified in-
terrupt.
Of course, interrupt’s priority is fixed by H/W, but some-
times user want to get specified interrupt even if higher
priority interrupt was occured. Higher priority interrupt is
processed the next time.
It contains 2bit data to enable priority selection and 4bit
data to select specified interrupt.
Figure 19-1 Interrupt Mode Register
Reset/Interrupt
Symbol
Priority
Hardware Reset
External Interrupt 0
OSD Interrupt
External Interrupt 1
External Interrupt 2
Timer/Counter 0
Timer/Counter 2
1 Frame Interrupt
VSync Interrupt
Timer/Counter 1
Timer/Counter 3
Interrupt interval measure
Watchdog Timer
Basic Interval Timer
Serial I/O Interrupt
I
2
C Interrupt
RESET
INT0
OSD
INT1
INT2
Timer 0
Timer 2
1Frame
VSync
Timer 1
Timer 3
INTV(INT3/4)
WDT
BIT
SIO
I2C
-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Bit No.
Name
Value
Function
5,4
IM1~0
00
01
1X
Mode 0: H/W priority
Mode 1: S/W priority
Interrupt is disabled, even
if IE is set.
3~0
IP3~0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
INT0
OSD
INT1
INT2
Timer 0
Timer 2
1Frame
VSync
Timer 1
Timer 3
INTV(INT3/4)
WDT
BIT
SIO
I2C
Not used
Table 19-1 Bit function
IMOD
ADDRESS : 00F3
RESET VALUE : Undefined
RW
RW
RW
IM0
IP3
IP2
IP1
IP0
RW
RW
RW
IM1
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