參數(shù)資料
型號(hào): HMS81C43XX
廠商: Hynix Semiconductor Inc.
英文描述: CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER FOR TELEVISION
中文描述: CMOS單芯片8位單片機(jī)電視
文件頁數(shù): 76/100頁
文件大小: 1943K
代理商: HMS81C43XX
HMS81C43xx / GMS87C4060
76
November 2001 ver 1.2
19.4 External Interrupt
The external interrupt on INT0, INT1... pins are edge trig-
gered depending the edge selection register.
Refer to “6. PORT STRUCTURES” on page 10.
The edge detection of external interrupt has three transition
activated mode: rising edge, falling edge, both edge.
Figure 19-8 External Interrupt Block Diagram
INT0, INT1 and INT2 are multiplexed with general I/O
ports. To use external interrupt pin, the bit of port function
register FUNC1 should be set to "1" correspondingly.
Response Time
The INT0, INT1 and INT2 edge are latched into INT0IF,
INT1IF and INT2IF at every machine cycle. The values
are not actually polled by the circuitry until the next ma-
chine cycle. If a request is active and conditions are right
for it to be acknowledged, a hardware subroutine call to the
requested service routine will be the next instruction to be
executed. For example, the DIV instruction takes twelve
machine cycles. Thus, a minimum of twelve complete ma-
chine cycles elapse between activation of an external inter-
rupt request and the beginning of execution of the first
instruction of the service routine
Figure 19-9 Interrupt Response Timing Diagram ( Interrupt overhead )
INT0IF
INT0 pin
INT0 INTERRUPT
INT1IF
INT1 pin
INT1 INTERRUPT
INT2IF
INT2 pin
INT2 INTERRUPT
IEDS
[00F2
H
]
e
System clock
Instruction Fetch
Last instruction execution (0~12cycle)
Enter interrupt service routine (8cycle)
Interrupt request sampling
1cycle
Interrupt overhaed (9~21cycle)
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