參數(shù)資料
型號： HMS81C43XX
廠商： Hynix Semiconductor Inc.
英文描述： CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER FOR TELEVISION
中文描述： CMOS單芯片8位單片機(jī)電視
文件頁數(shù)： 78/100頁
文件大?。?/td> 1943K
代理商： HMS81C43XX
HMS81C43xx / GMS87C4060
78
November 2001 ver 1.2
Example: Sets the watchdog timer detection time
Enable and Disable Watchdog
Watchdog timer is enabled by setting WDTON (bit 5 in
CKTCLR) to "1". WDTON is initialized to "0" during re-
set, WDTON should be set to "1" to operate after reset is
released.
Example: Enables watchdog timer reset
:
LDM
:
:
CKTCLR,#001b ;WDTON
←
1
The watchdog timer is disabled by clearing bit 5 (WD-
TON) of CKTCLR.
Watchdog Timer Interrupt
The watchdog timer can also be used as a simple 6-bit tim-
er by clearing bit 5 (WDTON) of CKTCLR. The interval
of watchdog timer interrupt is decided by Basic Interval
Timer.
Interval equation is shown as below.
The stack pointer (SP) should be initialized before using
the watchdog timer output as an interrupt source.
Example: 6-bit timer interrupt setting up.
LDX
TXSP
LDM
LDM
:
:
#03FH
;SP
←
3F
CKTCLR,#000b ;WDTON
←
0
WDTR,#01b ;WDTCL
←
0
Refer table and see BIT timer ().
LDM
WDTR,#01b
;
Clear Counter and set value(b)
;
You have to set WDTR first, for prevent unpredictable interrupt
;
when you set WDTON bit.
;
Select clock source(b)
and WDTON=1
LDM
CKCTLR,#00111b
LDM
:
:
:
:
LDM
:
:
:
:
LDM
WDTR,#01b
;
Clear counter
WDTR,#01b
;
Clear counter
WDTR,#01b
;
Clear counter
Within WDT
detection time
Within WDT
detection time
×
=
CKCTLR
BTS2~0
BIT input
clock
Watchdog
timer input
clock
IFWDT cycle
000
b
PS4 (2uS)
512uS
32,256uS
001
b
PS5 (4uS)
1,024uS
64,512uS
010
b
PS6 (8uS)
2,048uS
129,024uS
011
b
PS7 (16uS)
4,096uS
258,048uS
100
b
PS8 (32uS)
8,192uS
516,096uS
101
b
PS9 (64uS)
16,384uS
1,032,192uS
110
b
PS10 (128uS)
32,768uS
2,064,384uS
111
b
PS11 (256uS)
65,536uS
4,128,768uS
Table 20-1 Watchdog timer MAX. cycle (Ex:f
ex
=8MHz)
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