參數(shù)資料
型號(hào)： HMS81C43XX
廠商： Hynix Semiconductor Inc.
英文描述： CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER FOR TELEVISION
中文描述： CMOS單芯片8位單片機(jī)電視
文件頁(yè)數(shù)： 40/100頁(yè)
文件大?。?/td> 1943K
代理商： HMS81C43XX
HMS81C43xx / GMS87C4060
40
November 2001 ver 1.2
Figure 11-8 Simplified Block Diagram of 16bit Timer/Event Counter 2,3
Timer Mode
In the timer mode, the internal clock is used for counting
up. Thus, you can think of it as counting internal clock in-
put. The contents of TDRn (n=0~3) are compared with the
contents of up-counter, Timer n. If match is found, a timer
n interrupt (TnIF) is generated and the up-counter is
cleared to 0. Counting up is resumed after the up-counter
is cleared.
As the value of TDRn is changeable by software, time in-
terval is set as you want
Figure 11-9 Timer Mode Timing Chart
Event counter Mode
In event timer mode, counting up is started by an external
trigger. This trigger means falling edge of the ECn (n=2~3)
pin input. Source clock is used as an internal clock selected
with TM2. The contents of TDRn are compared with the
contents of the up-counter. If a match is found, an TnIF in-
terrupt is generated, and the counter is cleared to 00
H
. The
counter is restarted by the falling edge of the ECn pin in-
put.
The maximum frequency applied to the ECn pin is f
ex
/2
[Hz] in main clock mode.
In order to use event counter function, the bit EC2S, EC3
of the Port Function Select Register1 FUNC1(address
0CE
H
) is required to be set to "1".
After reset, the value of TDRn is undefined, it should be
Internal bus line
TM2
TDR2
Timer 2
Clock
TDR3
Timer 3
Clock
Clear
Clear
16bit Comparator
T3IF
MUX
EC2
PS4
PS6
PS8
T0CN
T0ST
0
0
0
N-2
2
0
N
3
N-1
N
~
~
~
Source clock
Up-counter
TDRn (n=0~3)
TnIF (n=0~3) interrupt
Start count
~
1
2
3
~
~
1
4
Match
Detect
Counter
Clear
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