參數(shù)資料
型號： HMS81C43XX
廠商： Hynix Semiconductor Inc.
英文描述： CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER FOR TELEVISION
中文描述： CMOS單芯片8位單片機(jī)電視
文件頁數(shù)： 64/100頁
文件大?。?/td> 1943K
代理商： HMS81C43XX
HMS81C43xx / GMS87C4060
64
November 2001 ver 1.2
Figure 18-2 I
2
C address Register
I
2
C data shift register [ICDR]
The I
2
C data shift register is an 8bit shift register to store
received data and write transmit data.
When transmit data is written into this register, it is trans-
fered to the outside from bit7 in synchronization with the
SCL clock, and each time one-bit data is output, the data of
this register are shifted one bit to the left. When data is re-
ceived, it is input to this register from bit0 in synchroniza-
tion with the SCL clock, and each time one-bit data is
input, the data of this register are shifted one bit to the left.
The I
2
C data shift register is in a write enable status only
when the ESO bit of the I
2
C control register (address
00DC
H
) is “1”. The bit counter is reset by a write instruc-
tion to the I
2
C data shift register. Reading data from the
I
2
C data shift register is always enabled regardless of the
ESO bit value.
Figure 18-3 Data shift register
I
2
C status register
The I
2
C status register controls the I
2
C Bus interface sta-
tus. The low-order 4bits are read only bits and the high-or-
der 4bits can be read out and written to.
The more details about its bits are shown Table 18-1.
ICAR
ADDRESS : 00D8
RESET VALUE : 0000 0000
b
RW
RW
R
SAD6 SDA5 SDA4 SDA3 SDA2 SDA1 SDA0 R/W
Slave address
RW
RW
RW
RW
RW
ICDR
ADDRESS : 00D9
RESET VALUE : 0000 0000
b
RW
RW
RW
RW
RW
RW
RW
RW
D7
D6
D5
D4
D3
D2
D1
D0
Shift left 1-bit each SCL
Bit
No.
Name
Function
7
6
MST
TRX
00: Slave / Receiver mode
01: Slave / Transmitter mode
10: Master / Receiver mode
11: Master / Transmitter mode
MST is cleared when
- After reset.
- After the arbitration lost is occured and
1 byte data transmission is finished.
- After stop condition is detected.
- When start condition is disabled by
start condition duplication preventation
function.
TRX is cleared when
- After reset.
- When arbitration lost or stop condition
is occured .
- When MST is ‘0’, and start condition
or ACK non-return mode is detected.
5
BB
BB(Bus busy)bit is 1 during bus is busy.
This bit can be written by S/W. its value
is ‘1’ by start condition, and cleared by
stop condition.
4
PIN
PIN(Pending Interrupt Not)bit is inter-
rupt request bit.
If I
2
C interrupt request is issued, its
value is 0.
PIN is cleared when
- After 1 byte trasmission / receive is fin-
ished.
PIN is set when
- After reset.
- After write instruction is excuted into
I
2
C data shift register ICDR.
- When PIN bit low, the output of SCL is
pulled down, So if you want to release
SCL, you must perform write instruction
CDR.
3
AL
Arbitration lost detection flag.
If arbitration lost is detected, AL=1, or 0.
2
AAS
Slave address comparison flag.
It shows compared result with received
address data and I
2
C address register
(ICAR).
It is 1, when two of data is same.
Table 18-1 Bit function
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