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參數(shù)資料
| 型號： | HMS81C43XX |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER FOR TELEVISION |
| 中文描述： | CMOS單芯片8位單片機電視 |
| 文件頁數(shù)： | 34/100頁 |
| 文件大小： | 1943K |
| 代理商： | HMS81C43XX |
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HMS81C43xx / GMS87C4060
34
November 2001 ver 1.2
10. CLOCK GENERATOR
As shown in Figure 10-1 , the clock generator produces the
basic clock pulses which provide the system clock to be
supplied to the CPU and the peripheral hardware. It con-
tains two oscillators: a main-frequency clock oscillator and
a sub-frequency clock oscillator. The system clock can
also be obtained from the external oscillator.
The clock generator produces the system clocks forming
clock pulse, which are supplied to the CPU and the periph-
eral hardware.
To the peripheral block, the clock among the not-divided
original clocks, divided by
2
, 4,...,
up to 1024 can be pro-
vided. Peripheral clock is enabled or disabled by bit 4 of
the peripheral clock enable register (ENPCK).
Figure 10-1 Block Diagram of Clock Generator
Note:
On the initial reset, all peripherals are run because
peripheral clock is supplied to each function block. If you
want to see more details, see Clock Control Register
(CKCTLR).
Main clock
Minimum instruction cycle time
(ex:NOP ; f
ex
4clock is needed)
3.6MHz
1,111nS
4MHz
1,000nS
8MHz
500nS
Internal system clock
PRESCALER
ENPCK
1
Peripheral clock
f
EX
Clock control register
[0D6
H
]
CKCTLR
ON
BTS2
BTS1 BTS0
Clock pulse Generator
OSC
Circuit
P
P
P
P
P
P
P
P
P
P
P
1
P
2
2
4
8
1
3
6
1
2
5
Test mode register
ADDRESS : 00FD
RESET VALUE : 0000 0000
b
W
W
W
TMR
W
W
W
W
W
0000 0110b Normal operation mode
Clock control register
ADDRESS : 00D6
RESET VALUE : --01 0111
b
W
W
W
CKCTLR
Watch-dog
timer select
0: Normal 6bit timer
1: Watch-dog timer
ON
BTS1
BTS0
Peri. Clock
0: Stop
1: Supply
B.I.T set
0: Free run
1: B.I.T clear
B.I.T Clock
W
W
W
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|---|---|
| HMS81C4460 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS |
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