參數(shù)資料
型號(hào): HMS30C7110
廠商: Electronic Theatre Controls, Inc.
元件分類: 網(wǎng)絡(luò)處理器
英文描述: Multipurpose Network Processor
中文描述: 多功能網(wǎng)絡(luò)處理器
文件頁數(shù): 90/161頁
文件大小: 973K
代理商: HMS30C7110
HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
90
1920_108C
Bits
Access Default Description
31:24 RW
0
Byte 3 of the Ethernet MAC address
23:16 RW
0
Byte 2 of the Ethernet MAC address
15:8
RW
0
Byte 1 of the Ethernet MAC address
7:0
RW
0
Byte 0 of the Ethernet MAC address
2.6.2.22.
P_FRM_ADDR_0 (offset = 0x90)
This register along with the P_FRM_ADDR 1 register (offset 0x94) forms a 6-byte address field of
an Ethernet Pause frame. It also provides byte ordering and valid bits for configuration.
Table 2.44 Pause Frame Address 0
MAC0 Address :
1920_0090
MAC1 Address :
1920_1090
Bits
Access Default Description
31:24 RW
0
Reserved
23:21 RW
0
Reserved
20
RW
0
Byte ordering
0 = Byte 5 is the most significant byte of the address
1 = Byte 0 is the most significant byte of the address
19:17 RW
0
Reserved
16
RW
0
VALID
0 = The address will not be compared with incoming destination address
1 = The address will be compared with incoming destination address
15:8
RW
0x01
Byte 5 of the Pause Frame Multicast address
7:0
RW
0x80
Byte 4 of the Pause Frame Multicast address
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