參數(shù)資料
型號(hào)： HMS30C7110
廠商： Electronic Theatre Controls, Inc.
元件分類： 網(wǎng)絡(luò)處理器
英文描述： Multipurpose Network Processor
中文描述： 多功能網(wǎng)絡(luò)處理器
文件頁數(shù)： 129/161頁
文件大小： 973K
代理商： HMS30C7110
HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
129
This register is used to mask the requests of some interrupt sources. If a bit of the register is set to 1,
it indicates that the corresponding interrupt is disabled. If it is set to 0, the corresponding interrupt
will be serviced normally. This mask register actually resides after the SRCPND register and affects
the effective value of SRCPND register going to arbitration logic and NMI generation logic.
Therefore, even for the masked requests, SRCPND register reflects their arrival as usual.
Interrupt Sources
Interrupt controller supports 21 interrupt sources as shown in the below table.
Table 2.96 Interrupt Source Register
Sources
Bit
Descriptions
Arbiter Group
INT_UART1
29
UART1 interrupt
ARB5
INT_UART0
28
UART0 interrupt
ARB5
INT_SPI
27
SPI interrupt
ARB4
Reserved
26
Reserved
ARB4
CardBus
22
CardBus error interrupt
ARB4
CARD IRQ
21
IRQ from installed Card
ARB3
PCMCIA
20
PCMCIA
interrupt
including
card
detection
ARB3
INT_GPIO
19
GPIO interrupt (from GPI8 ~ GPI10)
ARB3
INT_DMA1
18
DMA channel 1 interrupt
ARB3
INT_DMA0
17
DMA channel 0 interrupt
ARB3
INT_ENET1
14
ENET MAC 1 interrupt
ARB2
INT_ENET0
11
ENET MAC 0 interrupt
ARB2
INT_TIMER
10
TIMER interrupt
ARB2
INT_EXT7
7
External interrupt 7 (from GPI7)
ARB1
INT_EXT6
6
External interrupt 6 (from GPI6)
ARB1
INT_EXT5
5
External interrupt 5 (from GPI5)
ARB1
INT_EXT4
4
External interrupt 4 (from GPI4)
ARB1
INT_EXT3
3
External interrupt 3 (from GPI3)
ARB0
INT_EXT2
2
External interrupt 2 (from GPIO2)
ARB0
INT_EXT1
1
External interrupt 1 (from GPIO1)
ARB0
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