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HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
10
Table 2.101 DMA Mask Trigger Register................................................................126
Table 2.102 Interrupt Source Register.....................................................................129
Table 2.103 Source Pending Register......................................................................132
Table 2.104 Interrupt Mode Register.......................................................................133
Table 2.105 Interrupt Mask Register .......................................................................133
Table 2.106 Priority Register ...................................................................................134
Table 2.107 Interrupt Pending Register...................................................................135
Table 2.108 Interrupt Offset Register......................................................................136
Table 2.109 Registers for PCMCIA..........................................................................137
Table 2.110 Registers for CardBus..........................................................................138
Table 2.111 IDR Bit Definition..................................................................................138
Table 2.112 ISR Bit Definition ..................................................................................139
Table 2.113 ICR Bit Definition..................................................................................139
Table 2.114 GCR Bit Definition.................................................................................140
Table 2.115 CSCR Bit Definition ..............................................................................141
Table 2.116 IER Bit Definition..................................................................................141
Table 2.117 Setup Bit Definition ..............................................................................142
Table 2.118 Command Bit Definition........................................................................142
Table 2.119 Recovery Bit Definition........................................................................143
Table 2.120 Start Address Bit Definition.................................................................144
Table 2.121 End Address Bit Definition...................................................................144
Table 2.122 GPIO direction registers Bit Definition ...............................................145
Table 2.123 GPO registers Bit Definition ................................................................145
Table 2.124 GPI registers Bit Definition..................................................................145
Table 2.125 GPIO muxing table................................................................................146
Table 2.126 Command Bit Definition........................................................................147
Table 2.127 Status Bit Definition..............................................................................148
Table 2.128 Retry time register Bit Definition........................................................149
Table 2.129 Clk select register Bit Definition.........................................................149
Table 3.1 Absolute maximum ratings.......................................................................150
Table 3.2 Recommended operating conditions........................................................150
Table 3.3 DC Characteristics....................................................................................151
Table 3.4 A.C. Electrical Characteristics.................................................................158