參數(shù)資料
型號: HMS30C7110
廠商: Electronic Theatre Controls, Inc.
元件分類: 網(wǎng)絡(luò)處理器
英文描述: Multipurpose Network Processor
中文描述: 多功能網(wǎng)絡(luò)處理器
文件頁數(shù): 81/161頁
文件大小: 973K
代理商: HMS30C7110
HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
81
Bits
Access Default Description
31:0
RW
0x0
Transmit buffer start address
2.6.2.7.
TX_LENGTH (offset = 0x18)
The total frame length (starting from destination address to the end of frame, excluding CRC field)
should be written to this register.
Table 2.29 Transmit Buffer Length
MAC0 Address :
1920_0018
MAC1 Address :
1920_1018
Bits
Access Default Description
31:16 RW
0x00
Reserved
15:0
RW
0x00
Transmit buffer length in bytes
2.6.2.8.
RX_BADDR (offset = 0x1C)
The starting address of RX buffer to store incoming frame is written to this register. RX_BADDR
can hold 15 entries of the start address of RX buffer. The number of entries not taken for RX
processing can be read from bits[10:8] of RX_BUFLVL (offset = 0x24). Not assigning a buffer
address in time will result in an interrupt (if enabled) with INT_SRC bit[5] and the frame will be
dropped.
Table 2.30 Receive Buffer Address
MAC0 Address :
1920_001C
MAC1 Address :
1920_101C
Bits
Access Default Description
31:0
RW
0x00
Receive buffer start address
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