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參數(shù)資料
| 型號(hào)： | HMS30C7110 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 網(wǎng)絡(luò)處理器 |
| 英文描述： | Multipurpose Network Processor |
| 中文描述： | 多功能網(wǎng)絡(luò)處理器 |
| 文件頁(yè)數(shù)： | 128/161頁(yè) |
| 文件大小： | 973K |
| 代理商： | HMS30C7110 |
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HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
128
2.12.
INTC
The interrupt controller of HMS30C7110 receives the request from 21 interrupt sources. Among
21, 8 come from outside of chip, i.e., external interrupt sources, and remaining 13 come from
internal sources such as DMA controller, ENET MAC, and etc.
The role of the interrupt controller is to ask for IRQ and/or NMI to the ARM7TDMI after selecting
one among 21 sources based on the arbitration rule. The arbitration is performed by the hardware
priority logic and the result is written to the interrupt pending register to let users to know which
interrupt has been requested.
Interrupt Mode
INTC supports 2 types of interrupt modes, NMI and IRQ. The mode of each interrupt source can be
set by programming interrupt mode register. Among 21 sources, only one, generally very urgent one
such as power failure can be set to operate as NMI.
Interrupt Pending Register
There are two interrupt pending registers. One is source pending register (SRCPND) and the other
is interrupt pending register (INTPND). These pending registers indicate whether or not an interrupt
request is pending. When the interrupt sources request interrupt services the corresponding bits of
SRCPND register are set to 1, and at the next clock cycle one bit of INTPND register corresponding
to the highest priority one is set to 1 after the arbitration process. If some of interrupts are masked
(by programming mask register), the corresponding bits of INTPND register are not set to 1, while
the corresponding bits of SRCPND register are set to 1. When a pending bit of INTPND register is
set, IRQ is generated and goes to CPU. The SRCPND and INTPND registers can be read and
written. The interrupt service routine must clear the pending condition by writing a 1 to the
corresponding bit of SRCPND register first and then clear the pending condition in INTPND
registers by writing 1.
The NMI shares the SRCPND register with IRQ, but it does not go through the arbitration logic and
directly goes to CPU for a fast service. So, in the service routine of NMI, user needs to clear only
the SRCPND register.
Interrupt Mask Register
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HMS30C2000 | [Application Specific Solution Product] |
| HMS30C7210 | ARM Based 32-Bit Microprocessor |
| HMS30C7080 | Mobile Phone Camera Back-End Processor |
| HMS30C7202 | 32-bit ARM7TDMI RISC static CMOS CPU core |
| HMS30C7202N | Highly-intergrated MPU |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HMS30C7202 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:32-bit ARM7TDMI RISC static CMOS CPU core |
| HMS30C7202N | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Highly-intergrated MPU |
| HMS30C7210 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ARM Based 32-Bit Microprocessor |
| HMS3224M3 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:SRAM MODULE 768KBit (32K x 24-Bit) |
| HMS3224M3-10 | 制造商:HANBIT 制造商全稱:Hanbit Electronics Co.,Ltd 功能描述:SRAM MODULE 768KBit (32K x 24-Bit) |
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