參數(shù)資料
型號(hào): HMS30C7110
廠商: Electronic Theatre Controls, Inc.
元件分類: 網(wǎng)絡(luò)處理器
英文描述: Multipurpose Network Processor
中文描述: 多功能網(wǎng)絡(luò)處理器
文件頁數(shù): 141/161頁
文件大?。?/td> 973K
代理商: HMS30C7110
HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
141
2.13.1.5.
Card Status Change Register (CSCR)
Table 2.109 CSCR Bit Definition
Address :
1940_0010
Bits
Access Default Description
31:4
0x00
Reserved
3
ROC
0x
Card Detect Change Detected
This bit will be set when a transition (low to high or high to low) has
occurred on the CD2~1 pins. This bit is reset to 0 when this register
is read.
2
ROC
0x0
Ready Change Detected
This bit will be set when a transition (low to high or high to low) has
occurred on the READY pin. This bit is reset to 0 when this register
is read.
This bit has meaning only when the socket is configured for the
memory-only interface. In the I/O and memory interface it reads
back as 0.
1
0x0
Reserved
0
ROC
0x0
Status Change Detected
This bit will be set when a transition (low to high or high to low) has
occurred on the STSCHG pin. This bit is reset to 0 when this register
is read.
2.13.1.6.
Interrupt Enable Register (IER)
Table 2.110 IER Bit Definition
Address :
1940_0014
Bits
Access Default Description
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