參數(shù)資料
型號: HMS30C7110
廠商: Electronic Theatre Controls, Inc.
元件分類: 網(wǎng)絡處理器
英文描述: Multipurpose Network Processor
中文描述: 多功能網(wǎng)絡處理器
文件頁數(shù): 88/161頁
文件大?。?/td> 973K
代理商: HMS30C7110
HMS30C7110
2003 MagnaChip Semiconductor Ltd. All Rights Reserved
Version 1.5
88
Frames with payload of more than this value will be truncated.
15:8
RW
0x2e
Minimum payload length, default = 46 in decimal
7:0
RW
0x10
Maximum burst transfer length in word on the system bus.
default = 16 in decimal
2.6.2.18.
MCAST_ADDR_0 (offset = 0x48)
This register combined with MCAST_ADDR_1 (offset = 0x4C) provides 64-bit field to qualify
multicast frame destined to this Ethernet MAC. Only one bit out of 64-bits should be set to
determine valid multicast address. The bit position to be set is calculated by applying CRC over
destination address field of incoming multicast frame.
Table 2.40 Multicast Address (Most Significant)
MAC0 Address :
1920_0048
MAC1 Address :
1920_1048
Bits
Access Default
Description
31:0
RW
0
Only one bit position should be set to determine that the current
multicast frame is destined to this MAC
2.6.2.19.
MCAST_ADDR_1 (offset = 0x4c)
Table 2.41 Multicast Address (Least Significant)
MAC0 Address :
1920_004C
MAC1 Address :
1920_104C
Bits
Access Default
Description
31:0
RW
0
See Multicast Address 0 (offset = 0x48)
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