![](http://datasheet.mmic.net.cn/280000/HM17CM4096_datasheet_16072211/HM17CM4096_35.png)
HM17CM4096
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(13) DISPLAY TIMMING GENERATOR
The display-timing generator makes a timing clock and timing pulses (CL, FLM, FR and CLK) for
internal operation by inputting the original oscillating clock CK or by the oscillating circuit.
(14) SIGNAL GENERATION OF DISPLAY LINE COUNTER, DISPLAY DATA LATCH CIRCUIT.
The latch signal from line counter clock to display data latch circuit is generated from display clock
(CL). Synchronized with the display clock, the line addresses of Display RAM are generated and
384-bit display data are latched to display-data latching circuit and then output to the LCD drive
circuit (SEG output port).
Read-out of the display data to the LCD drive circuit is completely independent of MPU side and so
MPU can access it with no relationship with the read-out operation of the display data.
(15) GENERATION OF THE ALTERNATED SIGNAL(FR), SYNCHRONOUS SIGNAL(FLM).
The alternated signal (FR) and synchronous signal (FLM) are generated from the display clock
(CL). The FLM generates alternated drive waveform to the LCD drive circuit per frame at normal
state ( inverse FR signal level per 1 frame ). But by setting up data (n-1) on n-line inversion register
and “1” on n-line alternated command (NLIN), n-line inverse waveform can be generated.
(16) DISPLAY DATA LATCH CIRCUIT
This circuit latches the display data from display RAM to LCD driver circuit temporarily per every
common period. Normal / reverse display, display ON/OFF, and display all on command are done
by controlling data in this latch. And no data within display RAM changes.