
HM17CM4096
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Serial clock (SCL) should go to “L” at the non-access period and after 9bit data transfer.
SDA and SCL signals are sensitive to external noise. To prevent miss operation chip selector
state should be released (CS = “H”) after 9bit data transfer as shown in the following figure
.
3line serial interface
(1-7) One systematization of CS under some interface
In some operation mode, data interface control is possible.
Data in-out is possible under the condition, CS = “L”.
(2) DDRAM and internal register access
DDRAM and internal register are accessed by data bus D
0
~D
7
(D
0
~D
15
), chip select pin (CS),
DDRAM / register select pin (RS), read / write control pin (RD) or WR pin.
When CS=“H”, it is in non-selective state and DDRAM and internal register access is impossible.
During access, Set CS=“L”.
Access selection to DDRAM or internal register is controlled by RS input.
TABLE
RS
L
H
Data contents
Display RAM data
Internal command register
Write process starts after address setting and then the data on the 8bit data bus D
0
~D
7
or 16bit
data bus D
0
~D
15
will be written in by CPU. The data is written at the rising edge of WR (80 series) or
falling edge of E (68 series).
Internally, bus holder data is processed to data bus and data are written to bus holder from CPU
until next cycle.
After address setting, data of assigned address are read at the 1st and 3rd clock, which means it
needs dummy read at the 2nd clock.
There are rules at reading data out of display RAM, after address setting, the data of assigned
address is shown directly after the end of the read command, so pay attention that assigned data is
available at 2nd timing step.
In other words, 1 cycle dummy read is needed after address setting and write cycle.
RS
D
7
D
6
D
5
D
4
D
3
D
2
D
1
1
2
3
4
5
6
7
8
CS
SDA
SCL
D
0
9