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HM17CM4096
- 13 -
I
PIN DESCRIPTION 2
NAME
I/O
I/O
FUNCTION
D
8
,D
9
,D
10
,D
11
,
D
12
,D
13
,D
14
,D
15
Connect to data bus to MPU with 8bit bi-directional bus.
Used as MSB 8bit data bus in the 16bit data RAM transfer mode
Set to “L” or “H” when not used.
Chip selection pin.
Data in-out is possible when CS = “L”.
Input data selection pin.
Distinguish bus data from CPU whether instruction or display
data.
CS
I
RS
class
H
L
instruction
display data
RS
I
RD (E)
I
<80 series CPU interface (P/S=”H”,SEL68=”L”)>
RD signal connection port of 80 series CPU.
Data bus goes to output state at RD = “L”.
<68 series CPU interface (P/S=”H”,SEL68=”H”)>
Enable signal connection port of 68 series CPU.
Active status when this signal is at “H”.
<80 series CPU interface (P/S=”H”,SEL68=”L”)>
WR signal connection port of 80 series CPU.
Active at “L” and data bus signal is taken at the rising edge of
WR.
<68 series CPU interface (P/S=”H”,SEL68=”H”)>
Read write control signal , R/W connection port of 68-series
MPU.
H
R/W
status
L
read
write
WR (R/W)
I
CPU interface selection port
SEL68
status
Serial / parallel interface selection port
P/S
chip
select
command
H
CS
RS
L
CS
RS
P/S = “L” :serial interface selection ,D15~D5 goes to Hi-Z
state. Fix RD, WR to “H” or “L”.
Test port.
Fix to ”L”.
Latching signal pin of display data.
Display line counter is counted up at the rising edge and LCD
driving signal is generated at the falling edge
LCD synchronous signal (first line marker) I/O pin.
Display start address is loaded in the display line counter at
FLM = “H”.
Alternated display signal of LCD driver output I/O pin.
H
L
68 series
80 series
I
data/
data
read/
write
RD, WR
write only
serial clock
D
0
~D
7
SDA(D
1
)
-
SCL (D
0
)
P/S
I
u
TEST
I
CL
I/O
FLM
I/O
FR
I/O