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HM17CM4096
- 12 -
I
PIN DESCRIPTION 1
NAME
V
DD
V
SS
V
SSH
V
DDA
I/O
FUNCTION
supply
supply
supply
supply
Power pin for logic
GND pin for logic
High voltage GND pin
This pin is internally connected to V
DD
pin.
This pin is used when the voltage of each input pin is fixed to V
DD
level.
caution) Do not use to main power pin.
This pin is internally connected to V
SS
pin.
This pin is used when the voltage of each input pin is fixed to V
SS
level.
caution) Do not use to main power pin.
LCD driver supply voltage
LCD driver power supply port when external power supply is
used. When external power is used, voltages should have
following relations.
V
SS
<V
4
<V
3
<V
2
<V
1
<V
LCD
V
LCD
, V
1
~V
4
voltages are generated by voltage booster under
power circuit ON status.
When internal power supply is used, capacitors must be
connected between V
LCD
, V
1
~V
4
and V
SS
.
Capacitor connection pin for voltage converter
V
SSA
supply
V
LCD
V
1
V
2
V
3
V
4
supply/O
C
1
+
C
1
-
C
2
+
C
2
-
C
3
+
C
3
-
C
4
+
C
4
-
C
5
+
C
5
-
C
6
+
C
6
-
V
BA
V
REF
V
EE
O
O
Capacitor connection pin for voltage converter
O
Capacitor connection pin for voltage converter
O
Capacitor connection pin for voltage converter
O
Capacitor connection pin for voltage converter
O
Capacitor connection pin for voltage converter
O
I
Reference voltage output pin for voltage regulating.
Reference voltage input pin for voltage regulating.
Voltage supply pin for boosted voltage generation.
V
DD
level at normal status.
Internal DC/DC converter output pin.
Voltage regulator output pin.
Reset pin
Reset when RES= “L”
When parallel interface is selected (P/S=”H”), data line is
connected to MPU data bus with 8bit bi-directional bus
When serial interface is selected (P/S=”L”),
D
and D
(SCL, SDA) are used as serial interface pins and
various sets are taken by serial interface use mode of D
2
, D
3
,
D
4
.
SDA : serial data input pin
SCL : data transfer clock
EXCS : extension chip selection I/O pin
SMODE : serial transfer mode setting input pin
SPOL : RS polarity selection pin when 3 line serial interface is
selected.
SDA data is shifted at the rising edge of SCL
Internal serial/parallel conversion into 8-bit data occurs at the rising
edge of 8
th
clock of SCL.
Set to “L” after data transfer or during non-access time
supply
V
OUT
V
REG
supply/O
O
I
RES
D
0
/SCL
I/O
D
1
/SDA
I/O
D
2
/EXCS
I/O
D
3
/SMODE
I/O
D
4
/SPOL
I/O
D
5
,D
6
,D
7
I/O