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參數(shù)資料
| 型號： | HIP5061 |
| 廠商： | Intersil Corporation |
| 元件分類： | FPGA |
| 英文描述： | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 第7A，高效電流模式控制PWM穩(wěn)壓器 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 158K |
| 代理商： | HIP5061 |
7-57
HIP5061
MaxCI, Maximum Controllable Current
- The peak current
for the DMOS transistor when the Voltage-to-Current Con-
verter is at its full scale output. The DMOS transistor current
may exceed this value during the blanking time so proper
precautions should be taken. This parameter is unchanged
for the first 3/8 of the cycle and then decreases linearly with
time because of the Current Ramp becoming active.
Current Compensation Ramp
I/
t, Compensation Ramp Rate
- At a given voltage on V
C
the DMOS transistor will turn off at some current that stays
constant for about the first 1.5
μ
s of the cycle. After 1.5
μ
s, the
turnoff current starts to linearly decrease. This parameter
specifies the change in the DMOS transistor turnoff current.
t
RD
, Compensation Ramp Delay
- The time into each cycle
that the compensation ramp turns on. The Current Compen-
sation Ramp, used for Slope Compensation, is developed by
the Current Ramp block shown in the FUNCTIONAL BLOCK
DIAGRAM of Figure 2.
Start-Up
V
DDMIN
, Rising V
DD
Threshold Voltage
- The minimum
voltage on V
DD
needed to enable the IC.
V
DDHYS
, Power - On Hysteresis Voltage
- The difference
between the voltage on V
DD
that enables the IC and the volt-
age that disables the IC.
V
CEN
, Enable Comparator Threshold Voltage
- The mini-
mum voltage on V
C
needed to enable the IC. The IC can be
shutdown from an open-collector logic gate by pulling down
the V
C
pin to GND.
R
VC
, Power - Up Resistance
- When V
DD
is below V
DDMIN
,
the NMOS transistor connected to the V
C
pin is turned on to
make sure the V
C
node is low. Thus the voltage on V
C
can
gradually build up as will the trip current on the DMOS tran-
sistor. This is the only form of “soft start” included on the IC.
The resistance is measured between the V
C
and GND pins.
Thermal Monitor
T
J
, Rising Temperature Threshold
- The IC temperature
that causes the IC to disable itself so as to prevent damage.
Proper heat-sinking is required to avoid over-temperature
conditions, especially during start-up when the DMOS tran-
sistor may stay on for a long time if an external soft-start cir-
cuit is not added.
T
JHY
, Temperature Hysteresis
- The IC must cool down
this much after it is disabled by being too hot before it can
resume normal operation.
FIGURE 2. FUNCTIONAL BLOCK DIAGRAM OF THE HIP5061
GATE
DRIVER
BIAS
CIRCUITS
CURRENT
MONITORING
V
G
6
V
REF
= 5.1V
10.3V
V
DD
7
V
DD
SOURCE
DRAIN
5
TAB
+
-
ERROR
AMP
+
ENABLE
-
SOURCE
4
CONTROL
LOGIC
CLOCK
THERMAL
MONITOR
RAMP
CURRENT
COMPARE
1.5V
5.1V
V
REF
2K
360
HIP5061
CURRENT
+
-
+
SHORT
CIRCUIT
-
7.0V
V
DD
MONITOR
+
-
BLANKING
ENABLE
2K
CURRENT SAMPLE
RAMP ENABLE
RAMP RESET
ERROR CURRENT
100ns
UNDER VOLTAGE
LOCK OUT
V
DD
ERROR
AMP
DISABLE
GND
1
360
INTERNAL LEAD
INDUCTANCE
AND RESISTANCE
V
C
2
FB
3
V
CLAMP
BAND GAP
REFERENCE
REGULATOR
+
-
VOLTAGE TO
CURRENT
CONVERTER
LIGHT LOAD
COMPARATOR
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HIP5061DS | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP5062 | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP5062DW | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP5062DY | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP5063 | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HIP5061DS | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HIP5061DS WAF | 制造商:Harris Corporation 功能描述: |
| HIP5062 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Power Control IC Single Chip Dual Switching Power Supply |
| HIP5062DW | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Power Control IC Single Chip Dual Switching Power Supply |
| HIP5062DY | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Power Control IC Single Chip Dual Switching Power Supply |
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