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參數(shù)資料
| 型號(hào)： | HIP5061 |
| 廠商： | Intersil Corporation |
| 元件分類(lèi)： | FPGA |
| 英文描述： | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 第7A，高效電流模式控制PWM穩(wěn)壓器 |
| 文件頁(yè)數(shù)： | 3/20頁(yè) |
| 文件大小： | 158K |
| 代理商： | HIP5061 |
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Specifications HIP5061
CURRENT CONTROLLED PWM
g
m
(V
C
)
I
DRAIN, PEAK
/
V
C
Note 3
1.4
2.2
3.0
A/V
V/I
REF
Voltage to Current Converter Ref-
erence Voltage
I
DRAIN
= 0.25A, Note 3
2.4
2.8
3.1
V
t
BT
Current Comparator Blanking
Time
Note 3
40
100
175
ns
t
ONMIN
Minimum DMOS “ON” Time
Note 3
60
150
250
ns
t
OFFMIN
Minimum DMOS “OFF” Time
Note 3
40
125
200
ns
MinCI
Minimum Controllable DMOS
Peak Current
Note 3
-
100
250
mA
MaxCI
Maximum Controllable DMOS
Peak Current
Duty Cycle = 6% to 30%, Note 3
7
9.5
12
A
MaxCI
Maximum Controllable DMOS
Peak Current
Duty Cycle = 30% to 96%, Note 3
5
8
12
A
CURRENT COMPENSATION RAMP
I/
t
Compensation Ramp Rate
I
DRAIN, PEAK
/
Time, Note 3
-1.4
-0.85
-0.45
A/
μ
s
t
RD
Compensation Ramp Delay
Note 3
1.3
1.5
1.8
μ
s
START-UP
V
DDMIN
Rising V
DD
Threshold Voltage
V
FB
= 4V
9.3
10.3
10.8
V
V
DDHYS
Power-On Hysteresis
V
FB
= 4V
0.3
0.45
0.6
V
V
CEN
Enable Comparator Threshold
Voltage
1.0
1.5
2.0
V
R
VC
Power-Up Resistance
4V < V
DD
< 10.8V, V
C
= 0.8V
50
500
3000
THERMAL MONITOR
T
J
Substrate Temperature for
Thermal Monitor to Trip
Note 4
105
-
145
o
C
T
JHY
Temperature Hysteresis
Note 4
-
5
-
o
C
NOTES:
1. All Voltages relative to pin 1, GND.
2. V
D
= 10V, Starting T
J
= +25
o
C, L = 4mH, I
PEAK
= 7A.
3. Test is performed at wafer level only.
4. Determined by design, not a measured parameter.
Electrical Specifications
V
DD
= V
G
=12V, V
C
= 5V, V
FB
= 5.1V, SOURCE = GND = DRAIN = 0V, T
J
= 0
o
C to +105
o
C,
Unless Otherwise Specified
(Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
TABLE 1.
CONDITIONS FOR UNCLAMPED ENERGY CIRCUIT
V
D
(V)
I
L
(PEAK AMPS)
L (mH)
EAS (mJ)
10
5
40
550
10
7
4TZ
120
6
10
0.33
18
6
12.5
0.14
12
NOTE:
Device Selected to Obtain Peak Current without Clocking
FIGURE 1. UNCLAMPED ENERGY TEST CIRCUIT
VARY t
TO OBTAIN
REQUIRED PEAK I
L
12V
t
P
7
1
I
L
V
D
-
+
L
HIP5061
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HIP5061DS | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP5062 | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP5062DW | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP5062DY | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| HIP5063 | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HIP5061DS | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HIP5061DS WAF | 制造商:Harris Corporation 功能描述: |
| HIP5062 | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Power Control IC Single Chip Dual Switching Power Supply |
| HIP5062DW | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Power Control IC Single Chip Dual Switching Power Supply |
| HIP5062DY | 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:Power Control IC Single Chip Dual Switching Power Supply |
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