參數(shù)資料
型號(hào)： HIP5061
廠(chǎng)商： Intersil Corporation
元件分類(lèi)： FPGA
英文描述： FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN
中文描述： 第7A，高效電流模式控制PWM穩(wěn)壓器
文件頁(yè)數(shù)： 13/20頁(yè)
文件大?。?/td> 158K
代理商： HIP5061
7-65
HIP5061
the Current Ramp block is summed with the sensed DMOS
transistor current (to provide slope compensation) before
being compared with the Error Current signal. The current
ramp, -0.45A/
μ
s, is inhibited for the first 1.5
μ
s (37.5%) of the
duty cycle by the Ramp Enable signal, since ramp is not
needed for slope compensation during this interval. Inhibit-
ing of the compensating ramp has the effect of reducing the
peak short-circuit current.
The output of the power supply is divided down and
monitored at the FB terminal. A transconductance error
amplifier compares the DC level of the fed back voltage with
an internal bandgap reference, while providing voltage loop
compensation by means of external resistors and
capacitors. The Error Amplifier output (the error voltage) is
then converted into a current (the Error Current) that is used
to program the required peak DMOS transistor current that
produces the desired output voltage. When the sum of the
sensed DMOS transistor current and the compensating
ramp exceed the Error Current signal, the latch is reset and
the DMOS transistor is turned off. Current comparison
around this loop takes place in less than 50ns, allowing for
excellent 250kHz converter operation. The latch can also be
reset by an under-voltage (V
DD
< 10.3V typical), over
temperature (T
J
> +125
o
C typical) or a shutdown signal
externally applied at the V
C
terminal. See Figure 36.
Note that if the error voltage (at the V
C
pin) is less that
2.55V, then the output of the Voltage-to-Current Converter
will be held at zero. This condition will produce the minimum
possible pulse width, typically 150ns (100ns blanking pulse
plus 50ns delay). Error voltages lower than this 2.55V level
will not produce shorter pulse widths. Under very light loads
(when V
C
goes below 1.5V), the Enable Comparator will
temporarily hold-off the PWM latch (and the DMOS transis-
tor) until the V
C
voltages rises above 1.5V. This low V
C
inhibit circuit results in a burst-mode of operation that main-
tains regulation under light or no loads.
During an over-current condition, the output of the Error
Amplifier will attempt to exceed the 7.0V threshold. At this
point, the Short-Circuit Comparator will pull down on this sig-
nal and induce a low-level oscillation about the threshold,
serving to clamp the peak error voltage. This clamping
action, in turn, will limit the peak current in the DMOS tran-
sistor, reducing the duty ratio of the switch as the demand for
current continues to increase. This action, in conjunction
with the Thermal Monitor, serves to protect the IC from over-
current (short-circuit) conditions.
Using the Transconductance Error Amplifier
A transconductance amplifier with a typical g
m
of 30mS is
used as the input gain stage where the power supply output
voltage is compared with the internally generated 5.1V
reference voltage. A PNP transistor input structure allows
this amplifier to accommodate large negative going transient
voltages without causing amplifier phase reversal, often
associated with PNP input structures. Negative transients up
to 5V applied to the input though at least 5.1k will not result
in phase reversal. The amplifier output stage has the
customary drain to drain output to help improve the output
impedance, ideally infinity. The amplifier gain is typically
50dB and is not significantly altered when operating into the
stages that follow within the IC. To minimize the output stage
idling current, while providing high peak currents to insure
rapid response to load and input transients, a class B type of
output stage was used in the amplifier. Placing a 100k
resistor from the amplifier output terminal, V
C
, to ground will
bias the output stage to an active state and still minimize
power consumption. In all cases, the resistor shunting the
transconductance amplifier output must be greater than
10k
to insure that the output will rise sufficiently high to
obtain the maximum DMOS transistor drain current.
Start-Up Sequence
Upon initial power up of the HIP5061 in a typical application
circuit, the voltage at V
C
will be zero, and the DMOS transis-
tor will be off. When the voltage at V
DD
rises above the
10.3V typical threshold, the error amplifier output is enabled
and the V
C
voltage begins to rise in response to the low volt-
age at the FB terminal. When the V
C
voltage rises above
1.5V the DMOS transistor begins to switch at the minimum
duty cycle, and when it rises above 2.55V the duty cycle
begins to increase. The V
C
voltage (and peak DMOS tran-
sistor current) will then continue to rise until the voltage loop
gains control and establishes regulation. Note that the rate
of rise in the V
C
voltage can be controlled by an external soft
start circuit (See
Soft Start Implementation
).
If the V
C
voltage is unrestricted in its rate of rise, then it will
typically rise quickly to its maximum (peak current) value,
causing the DMOS transistor to turn-on and stay on until it
reaches the peak current value. At this point, the DMOS
transistor begins switching, and the V
C
voltage (and peak
DMOS transistor current) will drop down to the level com-
manded by the voltage loop.
Using the Shunt Regulator
The internal 14V shunt regulator in conjunction with an
external series resistor allows the IC to operate from quite
high input voltages, limited only by power dissipation in the
external resistor. When only higher voltages are available, a
bootstrap or other 12V auxiliary supply can be used to elimi-
nate this dissipation. The series resistor should be chosen to
be as large as possible to reduce power dissipation at high
line, while ensuring adequate V
DD
voltage at low line. The
maximum value for this resistor,
R
, is given by:
Where
V
I
is the input voltage to the power supply. The value
chosen for this resistor must also result in a current,
I
, into
the V
DD
clamp that is less than 105mA when the input volt-
age is at its maximum:
RMAX
(
)
,
----------------------------------------
10.5
–
=
IMAXA
,
13.3
–
-------------------------------------------------
=
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