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參數(shù)資料
| 型號： | HIP5061 |
| 廠商： | Intersil Corporation |
| 元件分類： | FPGA |
| 英文描述： | FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN |
| 中文描述： | 第7A，高效電流模式控制PWM穩(wěn)壓器 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大?。?/td> | 158K |
| 代理商： | HIP5061 |
7-66
HIP5061
Inductor Selection
The selection of the energy storage inductor(s) L
STOR
for a DC to
DC converter has tremendous influence on the behavior of the
converter. It is particularly important in light of the high level of
integration (and necessarily few degrees of freedom) achieved in
the HIP5061. There are several factors influencing the selection
of this inductor. First, the inductance of L
STOR
will determine the
basic mode of operation for the converter: continuous or
discontinuous current. In order to maximize the output power
for the given maximum controllable DMOS transistor current, a
converter may be designed to operate in continuous current
mode (CCM). However, this tends to require a larger inductor,
and for many converter topologies results in a feedback loop
tha is difficult to stabilize. For these and other reasons, the
inductor L
STOR
may be chosen so as to operate the converter in
discontinuous current mode (DCM). The relative merits of
CCM and DCM operation for various topologies and the
corresponding selection of L
STOR
is well documented and will not
be covered here.
A second factor influencing the selection of L
STOR
is the
stability requirement for current-mode control. This constraint is
only applicable for converters operating in CCM, since open-
loop instabilities of this type are not observed in converters
operating in DCM. For marginal stability, the compensating
ramp (internal to the HIP5061) must have a slope that is
greater than one-half the difference between the inductor
current’s down slope and up slope. (To ensure stability for duty
ratios D > 0.8, the slope of the compensating ramp should be
equal to the inductor current downslope.) A generally accepted
goal is to set the slope of the compensating ramp to be at least
one-half of the inductor current down slope. Since there is no
external control over the internal compensating ramp, one must
be sure that the inductor is large enough so that the down slope
of the inductor current is not too large. Table 2 summarizes this
requirement for minimum inductance for several common
topologies.
A third constraint on the size of the inductor is one that is
common among current-mode controlled PWM converters,
and applies to both DCM and CCM operation. The stable
generation of the desired DMOS transistor pulse width
depends on the accurate comparison of the error signal and
the peak L
STOR
(DMOS) transistor drain current. Thus, as
the peak L
STOR
ripple current becomes smaller, immunity
from noise on the error signal is eventually reduced until the
pulse width can no longer be adequately controlled. For the
HIP5061, the inductor current ripple must be at least 200mA
peak to peak to ensure proper control of the DMOS
transistor current. This effectively establishes a maximum
value for the inductor L
STOR
, so as to maintain at least
200mA of ripple. Note that under extremely light or no load
conditions, all converters will eventually operate in DCM,
and the 200mA requirement will eventually be violated.
Under these conditions, the HIP5061 will continue to
regulate, although the switching of the DMOS transistor will
be in a burst-mode, controlled by the Light Load
Comparator. (See Figure 2.)
DMOS Transistor Turn-Off Snubber
In order to reduce dissipation in the DMOS transistor due to
turn-off losses, the turn-off time has been minimized.
However, the rapid reduction of current that occurs in the
drain of the DMOS transistor can result in large transient
voltages being induced across any parasitic inductance in
the drain path. For this reason, it is important that such
parasitic inductance be reduced by good, high frequency
layout practices. Nevertheless, there are many instances
(e.g., transformer isolated topologies) in which voltages in
excess of 60V may be developed at the DMOS transistor
drain. In some cases, a simple R-C snubber may be added
to reduce the overshoot of the drain voltage to a safe level.
It is also possible that the large amount of ringing that can
occur at the DMOS transistor drain at turn-off will induce
noise in the IC. This noise may result in false triggering of
the PWM latch, particularly at high peak DMOS transistor
drain currents. Noise related instability can also be elimi-
nated by the addition of a snubber, which will rapidly damp
out such turn-off ringing. Good layout practices will reduce
the need for such protective measures, and ensure that the
DMOS transistor is not overstressed.
Under-Voltage Lockout
The V
DD
input voltage is monitored by a comparator that
holds off the DMOS transistor gate drive signal when the
V
DD
voltage is less that about 10.3V. The typical 0.5V hyster-
TABLE 2. MINIMUM INDUCTANCE FOR STABLE CCM
OPERATION ABOVE 50% DUTY CYCLE
CONVERTER TYPE
MINIMUM INDUCTANCE
Boost
SEPIC (Note 1)
Cuk (Note 2)
Flyback
Forward
NOTES:
1. Assumes that L
1
and L
2
are both CCM.
2. L = Inductance in Henrys, V
O
= Output Voltage,
V
D
= Diode Voltage Drop, V
I
= Input Voltage,
M
R,MIN
= (
I/
t)
MIN
= 0.45A/
μ
s, L
1
= Drain Inductor,
L
2
= Secondary Inductor, N
P
= Primary Turns,
N
S
= Secondary Turns
L
V
--------------M
V
R
, MIN
V
I
, MIN
–
+
=
L
L
1
+
L
2
L
V
R
, MIN
V
D
+
--M
>
L
L
1
+
L
2
L
V
R
, MIN
V
D
–
--M
>
L
P
N
P
N
S
------
V
R
, MIN
V
D
+
(
)
-----M
>
L
N
S
N
P
------
V
R
, MIN
V
D
+
(
------M
)
>
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