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參數(shù)資料

型號(hào)：	HIP5061
廠商：	Intersil Corporation
元件分類：	FPGA
英文描述：	FPGA 1000000 SYSTEM GATE 1.8 VOLT - NOT RECOMMENDED for NEW DESIGN
中文描述：	第7A，高效電流模式控制PWM穩(wěn)壓器
文件頁(yè)數(shù)：	4/20頁(yè)
文件大?。?/td>	158K
代理商：	HIP5061

7-56

HIP5061

Definitions of Electrical Specifications

Refer to the Functional Block Diagram of Figure 1 for loca-

tions of functional blocks and devices.

Device Parameters

I

DD

, Quiescent Supply Current

- Supply current with the

chip disabled. The Clock, Error Amplifier, Voltage-to-Current

Converter, and Current Ramp circuits draw only quiescent

current. The supply voltage must be kept lower than the

turn-on voltage of the V

DD

clamp or else the supply current

increases dramatically.

I

DD

, Operating Supply Current

- Supply current with the

chip enabled. The Error Amplifier is drawing its maximum

current because V

FB

is less than its reference voltage. The

voltage-to-current amplifier is drawing its maximum because

V

C

is at its maximum. The ramp circuit is drawing its maxi-

mum because it is not being disabled by the DMOS transis-

tor turning off.

IV

G

, Quiescent Gate Driver Current

- Gate Drivers supply

current with the IC disabled. The Gate Driver is not toggling

and so it draws only leakage current.

IV

G

, Operating Gate Driver Current

- Gate Drivers supply

current with the IC enabled. The DMOS transistor drain is

loaded with a large resistor tied to 60V so that it is swinging

from 0V to 60V during each cycle.

V

DDC

, V

DD

Clamp

- V

DD

voltage at the maximum allowed

current through the V

DD

Clamp.

V

REF

, Reference Voltage

- The voltage on FB that sets the

current on V

C

to zero. This is the reference voltage for the

DC/DC converter.

Amplifiers

|I

FB

|, Input Current

- Current through FB pin when it is at its

normal operating voltage. This current must be considered

when connecting the output of a DC/DC convertor to the FB

pin via a resistor divider.

g

m

(V

FB

), Transconductance

- The change in current

through the V

C

pin divided by the change in voltage on FB.

The g

m

times the resistance between V

C

and ground gives

the voltage gain of the Error Amplifier.

IV

CMAX

, Maximum Source Current

- The current on V

C

when FB is more than a few hundred millivolts less than

V

REF

.

IV

CMAX

, Maximum Sink Current

- The current on V

C

when

FB is more than a few hundred millivolts more than V

REF

.

A

OL

, Voltage Gain

- Change in the voltage on V

C

divided by

the change in voltage on FB. There is no resistive load on

V

C

. This is the voltage gain of the error amplifier when g

m

times load resistance is larger than this gain.

V

CMAX

, V

C

Rising Threshold

- The voltage on V

C

that

causes the Voltage-to-Current Amplifier to reach full-scale.

When V

C

reaches this voltage, the V

C

NMOS transistor (tran-

sistor with its drain connected to the V

C

pin in the Functional

Block Diagram of Figure 2) turns on and tries to lower the volt-

age on V

C

.

V

CHYS

, V

CMAX

Hysteresis

- The voltage on V

C

that causes

the NMOS transistor to turnoff if it had been turned on by V

C

exceeding V

CMAX

. At this voltage the current out of the Voltage-

to-Current Converter is at roughly three quarters of full-scale.

IVC

OVER

, V

C

Over-Voltage Current

- The current drawn

through the V

C

pin after the NMOS transistor is turned on

due to excessive voltage on V

C

. The NMOS transistor con-

nected to the V

C

pin draws more than enough current to

overcome the full scale source current of the Error Amplifier.

Clock

fq, Frequency

- The frequency of the DC/DC converter. The

Clock actually runs faster than this value so that various con-

trol signals can be internally generated.

DMOS Transistor

r

DS(ON)

, “On” Resistance

- Resistance from DMOS transis-

tor Drain to Source at maximum drain current and minimum

Gate Driver voltage, V

G

.

I

DSS

, Leakage Current

- Current through DMOS transistor

at the Maximum Rated Voltage.

Current Controlled PWM

g

m

(V

C

), Transconductance

- The change in the DMOS tran-

sistor peak drain current divided by the change in voltage on

V

C

. When analyzing DC/DC converters the DMOS transistor

and the inductor tied to the drain are sometimes modelled as

a voltage-controlled current source and this parameter is the

gain of the voltage-controlled current source.

V/I

REF

, Current Control Threshold

- The voltage on V

C

that causes the DMOS transistor to shut off at the minimum

controllable current. This voltage is greater than the Enable

Comparator Threshold (V

CEN

) so that as V

C

rises the IC

does not jump from the disabled state to the DMOS transis-

tor conducting a large current.

t

BT

, Blanking Time

- At the beginning of each cycle there is

a blanking time that the DMOS transistor turns-on and stays-

on no matter how high drain the current. This blanking time

permits ringing in the external parasitic capacitances and

inductances to dampen and for the charging of the reverse

bias on the rectifier diode.

t

ONMIN

, Minimum DMOS Transistor “On” Time

- The mini-

mum on-time for the DMOS transistor where small changes

in the V

C

voltage make predictable changes in the DMOS

transistor peak current. Converters should be designed to

avoid requiring pulse widths less than the minimum on time.

t

OFFMIN

, Minimum DMOS Transistor “Off” Time

- The min-

imum off-time for the DMOS transistor that allows enough time

for the IC to get ready for the next cycle. Converters should be

designed to avoid requiring pulse widths so large that the mini-

mum off time is violated. (However, zero off time is allowed, that

is, the DMOS transistor can stay on from one cycle to the next.)

MinCI, Minimum Controllable Current

- When the voltage

on V

C

is below V/I

REF

, the peak current for the DMOS tran-

sistor is too small for the Current Comparator to operate reli-

ably. Converters should be designed to avoid operating the

DMOS transistor at this low current.

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
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