參數(shù)資料
型號： HDMP-1014
英文描述： Bipolar Transistor; Collector Emitter Voltage, Vceo:400V; Transistor Polarity:N Channel; Power Dissipation:250W; C-E Breakdown Voltage:400V; DC Current Gain Min (hfe):10; Collector Current:50A; Package/Case:TO-3
中文描述： 4Low成本千兆速率發(fā)送/接收芯片組
文件頁數(shù)： 8/42頁
文件大小： 321K
代理商： HDMP-1014
580
HDMP-1014 Rx Block
Diagram
The HDMP-1014 receiver was
designed to convert a serial data
signal sent from the HDMP-1012
into either 16,17, 20 or 21 bit
wide parallel data. In doing this,
it performs the functions of
Clock Recovery
Data Recovery
Demultiplexing
Frame Decoding
Frame Synchronization
Frame Error Detection
Link State Control
Input Select
The input select block determines
which input line is used. In
normal operation (LOOPEN=0),
DIN is accepted as the input
signal. For improved distance
and BER using coax cable, an
input equalizer may be used by
asserting EQEN. By setting
LOOPEN high, the receiver
accepts LIN as the input signal.
This feature allows for loop back
testing exclusive of the
transmission medium.
Phase/Freq Detect
This block compares either the
phase or the frequency of the
incoming signal to the internal
serial clock, generated from the
Clock Select block. The
frequency detect disable pin
(FDIS) is set high to disable the
frequency detector and enable the
phase detector. See
HDMP-1014
(Rx) Phase Locked Loop
for
more details. The output of this
block, PH1, is used by the filter to
determine the control signal for
the VCO.
Filter
This is a loop filter that accepts
the PH1 output from the Phase/
Freq Detector and converts it into
a control signal for the VCO. This
control signal tells the VCO
whether to increase or decrease
its frequency. The Filter uses the
PH1 input to determine a
proportional signal and an
integral signal. The proportional
signal determines whether the
VCO should increase or decrease
its frequency. The integral signal
filters out the high frequency PH1
signal and stores a historical PH1
output level. The two signals
combined determine the
magnitude of frequency change of
the VCO.
VCO
This is the Voltage Controlled
Oscillator that is controlled by the
output of the Filter. It outputs a
high speed digital signal to the
Clock Select.
Figure 5. HDMP-1014 Receiver Block Diagram.
E
L
T
FLAG
CLOCK
SELECT
VCO
FILTER
PHASE /
FREQ
DETECT
INPUT
SELECT
CAP0
CAP1
0.1 μF
INPUT
SAMPLER
FRAME
DEMUX
CLOCK
GENERATOR
STATE
MACHINE
D-FIELD
DECODER
C-FIELD
DECODER
DAV*
CAV*
FF
LINKRDY*
STAT1
STAT0
D0..D19
DIN
LIN
T
D
D
S
S
A
FLAGSEL
ERROR
B
F
N
S
M
INTERNAL
CLOCKS
FDIS
PH1
相關PDF資料
PDF描述
HDMP-1022 Audio Power Amplifier; Speaker Channels:Mono; Headphone Channels:Mono; Output Power, Po:2W; Load Impedance Min:8ohm; Supply Voltage Max:24V; Supply Voltage Min:6V
HDMP-1024 Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價格千兆位速率接收芯片)
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HDMP-1034 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據速率的1.4 GBd 接收器)
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相關代理商/技術參數(shù)
參數(shù)描述
HDMP-1022 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os
HDMP-1024 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os
HDMP-1032 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate
HDMP-1032A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate
HDMP-1034 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate
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