- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370499 > HDMP-1014 Bipolar Transistor; Collector Emitter Voltage, Vceo:400V; Transistor Polarity:N Channel; Power Dissipation:250W; C-E Breakdown Voltage:400V; DC Current Gain Min (hfe):10; Collector Current:50A; Package/Case:TO-3 PDF資料下載
參數(shù)資料
| 型號： | HDMP-1014 |
| 英文描述： | Bipolar Transistor; Collector Emitter Voltage, Vceo:400V; Transistor Polarity:N Channel; Power Dissipation:250W; C-E Breakdown Voltage:400V; DC Current Gain Min (hfe):10; Collector Current:50A; Package/Case:TO-3 |
| 中文描述： | 4Low成本千兆速率發(fā)送/接收芯片組 |
| 文件頁數(shù)： | 11/42頁 |
| 文件大小： | 321K |
| 代理商： | HDMP-1014 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁當前第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
583
HDMP-1014 (Rx) Timing
Figure 7 is the Rx timing diagram
when the internal PLL is locked to
the incoming serial data. The
BCLK’s frequency is the same as
the input data rate. The size of
the input data frame can be either
20 bits or 24 bits, depending on
the setting of M20SEL.
Independent of the frame size,
STBROUT’s falling edge is aligned
to the data frame’s boundary,
while the rising edge is in the
center of the data frame.
The synchronous outputs, D00-
D19, LINKRDY*, DAV*, CAV*,
FF, ERROR, and FLAG, are
updated for every data frame,
with a delay of t
d1
after the falling
edge of STRBOUT. There is a
latency delay of two frames from
the input of the serial data frame
to the update of the synchronous
outputs.
The state machine outputs,
STAT0, and STAT1, appear with
the falling edge of STRBOUT after
a delay of td2. These outputs are
updated once every 128 frames.
HDMP-1014 (Rx) Timing Characteristics
Tc = 0
°
C to +85
°
C
Symbol
t
d1
t
d2
Parameter
Units
nsec
nsec
Min.
Typ.
2.0
4.0
Max.
Synchronous Output Delay
State Machine Output Delay
Figure 7. HDMP-1014 (Rx) Timing Diagram.
t
d2
t
d1
D-FIELD
C-FIELD
D00 - D19
LINKRDY*
DAV*, CAV*
FF, ERROR
FLAG
STRBOUT
DIN
BCLK
STAT1
STAT0
相關PDF資料 |
PDF描述 |
|---|---|
| HDMP-1022 | Audio Power Amplifier; Speaker Channels:Mono; Headphone Channels:Mono; Output Power, Po:2W; Load Impedance Min:8ohm; Supply Voltage Max:24V; Supply Voltage Min:6V |
| HDMP-1024 | Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價格千兆位速率接收芯片) |
| HDMP-1032 | 1.4 GBd Transmitter Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 傳送器) |
| HDMP-1034 | 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器) |
| HDMP-1512 | Fibre Channel Transmitter Chipset(光纖通道傳送芯片) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1022 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os |
| HDMP-1024 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os |
| HDMP-1032 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1032A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
發(fā)布緊急采購，3分鐘左右您將得到回復。