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參數(shù)資料
| 型號： | HDMP-1014 |
| 英文描述： | Bipolar Transistor; Collector Emitter Voltage, Vceo:400V; Transistor Polarity:N Channel; Power Dissipation:250W; C-E Breakdown Voltage:400V; DC Current Gain Min (hfe):10; Collector Current:50A; Package/Case:TO-3 |
| 中文描述： | 4Low成本千兆速率發(fā)送/接收芯片組 |
| 文件頁數(shù)： | 33/42頁 |
| 文件大?。?/td> | 321K |
| 代理商： | HDMP-1014 |
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605
Figure 16. Full Duplex Configuration.
Appendix II: Link
Configuration Examples
This section shows some
application examples using the
HDMP-1012/1014 chipset. Refer
to
I/O Definition
for detailed
circuit-level interconnection.
This guide is intended to aid the
user in designing G-LINK into a
system. It provides the necessary
details of getting the system up,
without the detailed description of
the inner circuitry of the chip set.
The first section is a description
of the various configurations for
duplex and simplex operation.
The second section describes the
interface to both single frame and
double frame mode. Following
that is a section on the integrating
capacitor and power supply
bypassing recommendations.
Next is a guide to the various
types of electrical I/O
connections. The final section is a
discussion on TTL translations
and the use of a single positive
supply. Also included is a list of
the various options and their
definitions.
Duplex/Simplex
Configurations
The following describes the
common setups for the link. In all
cases, the DIN and LIN are
differential high speed lines, and
unused leads should be
terminated with 50
AC coupled
to ground. Since the data stream
has no DC component, a coupling
cap of 0.1
μ
F is recommended for
the DIN and LIN inputs.
Full Duplex
Figure 16 shows HDMP-1012/
1014 in a full duplex configura-
tion connecting two bidirectional
(parallel) buses. Each end of the
link has a Tx and RX pair. The
receiver’s state machine outputs
(STAT0 and STAT1) are used to
control the status of the link.
Various options such as 16/20 bit
mode (M20SEL) and speed
selections (DIV0,DIV1) are
grouped together under the label
‘options’. A power-on reset is
available to the user to reset the
link during startup
Since the outputs STAT0 and
STAT1 are ECL levels, they can
be tied directly to the pins shown.
When the Tx has acquired lock to
the incoming STRBIN at the
frame rate, the LOCKED pin is
activated, which enables the Rx.
At this state, both STAT0 and
STAT1 are low, forcing the Tx to
send FF0, which is a square wave
pattern used by the remote Rx to
acquire frame lock. When the
local Rx has acquire frame lock,
STAT1 is set high to first turn off
its own frequency detector
(FDIS), then sets itself to active
mode (ACTIVE), and tells the
local Tx to send FF1 to signal the
remote Rx that the local pair is
ready. Likewise, when the remote
pair is ready, the local Rx will
Tx DATA
INTERFACE
DOUT
R
L
E
F
OPTIONS
Rx DATA
INTERFACE
DIN
A
F
S
S
S
S
LIN
Rx
Tx
Rx DATA
INTERFACE
LIN
S
S
S
S
F
A
DIN
Tx DATA
INTERFACE
LOUT
F
E
L
R
DOUT
Tx
Rx
POWER-ON
RESET
LOUT
POWER-ON
RESET
OPTIONS
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