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參數(shù)資料
| 型號： | HDMP-1014 |
| 英文描述： | Bipolar Transistor; Collector Emitter Voltage, Vceo:400V; Transistor Polarity:N Channel; Power Dissipation:250W; C-E Breakdown Voltage:400V; DC Current Gain Min (hfe):10; Collector Current:50A; Package/Case:TO-3 |
| 中文描述： | 4Low成本千兆速率發(fā)送/接收芯片組 |
| 文件頁數(shù)： | 4/42頁 |
| 文件大?。?/td> | 321K |
| 代理商： | HDMP-1014 |
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For timing diagrams for the
standard configurations, see the
Appendix section entitled
Link
Configuration Examples.
The HDMP-1012/1014 chipset
can support serial transmission
rates from 150 MBd to 1.5 GBd
for each of these configurations.
The chipset requires the user to
input the link data rate by
asserting DIV1 and DIV0
accordingly. To determine the
DIV1/DIV0 setting necessary for
each application, refer to the
section:
Setting the Operating
Data Rate Range
on the next
page.
Setting the Operating
Data Rate Range
The HDMP-1012/1014 chipset
can operate from 150 MBaud to
1500 MBaud. It is divided into
four operating data ranges with
each range selected by setting
DIV1 and DIV0 as shown in the
tables below.
The purpose of following example
is to help in understanding and
using these tables. This specific
example uses the table in figure 3
entitled “Typical 20-bit Mode Data
Rates”.
It is desired to transmit a 20 bit
parallel word operating at 55 MHz
(55 MWord/sec). Both the Tx and
Rx must be set to a range that this
word rate falls in-between.
According to table entitled
“Typical Operating Rates for 20
Bit Mode” on the next page, a
setting of DIV1/DIV0 = logic ‘0/0’
allows a parallel input word rate
of 32.9 to 62.5 MHz . This setting
easily accommodates the required
55 MHz word rate. The user serial
data rate can be calculated as:
Serial
Data Rate
20 bit
word
55 Mw
sec
= (––––––) (––––––)
= 1100 MBits/sec
The baud rate includes an
additional 4 bits that G-LINK
transmits for link control and
error detection. The serial baud
rate is calculated as:
Serial
Baud Rate
24 bits
word
55 Mw
sec
= (––––––) (––––––)
= 1320 MBaud
The 55 MHz example is one in
which the parallel word rate
provides only one possible DIV1/
DIV0 setting.
Some applications may have a
parallel word rate that seems to fit
two ranges. As an example, a 35
MHz (35 MWord/s) parallel data
rate fall within two ranges (DIV0/
DIV1 = 0/0 and DIV0/DIV1 = 0/
1) in 20 Bit Mode. Per the table, a
setting of DIV1/DIV0 = 0/1 gives
an upper rate of 53.3 MHz , while
a setting of DIV1/DIV0 = 0/0
gives a lower rate of 32.9 MHz.
These transition data rates are
stated in the tables as typical
values and may vary between
individual parts. Each transmitter/
receiver has continuous band
cover across its entire 150 to
1500 MBaud range and has
overlap between ranges. Each
transmitter/receiver will permit a
35 MHz parallel data rate, but it is
suggested that DIV0 be a jumper
that can be set either to logic ‘1’
(ground) or logic ‘0’ (open). This
allows the design to accommodate
both ranges for maximum
flexibility. This technique is
recommended whenever
operating near the maximum and
minimum of two word rate
ranges. The above information
also applies to the HDMP-1012/
1014 chipset when operating in
16 bit mode.
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| HDMP-1024 | Low Cost Gigabit Rate Receive Chip Set with TTL I/Os(帶TTL輸入/輸出的低價格千兆位速率接收芯片) |
| HDMP-1032 | 1.4 GBd Transmitter Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 傳送器) |
| HDMP-1034 | 1.4 GBd Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate(帶CIMT編碼器/譯碼器和變量數(shù)據(jù)速率的1.4 GBd 接收器) |
| HDMP-1512 | Fibre Channel Transmitter Chipset(光纖通道傳送芯片) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HDMP-1022 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os |
| HDMP-1024 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:Low Cost Gigabit Rate Transmit/Receive Chip Set with TTL I/Os |
| HDMP-1032 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1032A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:1.4 GBd Transmitter Chip with CIMT Encoder/Decoder and Variable Data Rate |
| HDMP-1034 | 制造商:AGILENT 制造商全稱:AGILENT 功能描述:1.4 GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate |
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