參數(shù)資料
型號(hào)： HDMP-1014
英文描述： Bipolar Transistor; Collector Emitter Voltage, Vceo:400V; Transistor Polarity:N Channel; Power Dissipation:250W; C-E Breakdown Voltage:400V; DC Current Gain Min (hfe):10; Collector Current:50A; Package/Case:TO-3
中文描述： 4Low成本千兆速率發(fā)送/接收芯片組
文件頁(yè)數(shù)： 37/42頁(yè)
文件大小： 321K
代理商： HDMP-1014
609
the flag input to signify the two
frames. The setup and hold times
are referenced to 1/2 frame
period of D0-D19, or 90 deg,
from the edges of STRBIN. The
multiplexer delay, t
mux
, should be
considered for timing margins.
The STRBOUT is derived from the
internal sampling clock, and thus
has a frequency double that of
STRBIN. The falling edge of
STRBOUT appears after the rising
and falling edges of STRBIN after
a delay of T
strb
. Other interlacing
techniques can also be achieved
with edge-triggered latches for
improved timing margins.
In the Rx side, the frame D0-D19
are demultiplexed back to the
original C0-C19, and C20-C39
frames with the use of external
edge-triggered flip-flops. The
toggle clock of the flip-flops,
RCLK, is derived by the state of
the FLAG bit. RCLK toggle with
the rising edge of STRBOUT with
a delay of t
da
. The two frames
appear with the rising and falling
edges of RCLK with a delay of t
db
.
All of the synchronous outputs
and state machine outputs appear
after the falling edge of STRBOUT
with delays of t
d1
and t
d2
respectively.
The lower frame of C0-C19 can
be delayed further with additional
latches so that both C0-C19 and
C20-C39 frames are synchronous.
Supply Bypassing and
Integrator Capacitor
Figure 20 shows the location of
the PLL integrator capacitors,
power supply capacitors and
required grounding for the Tx and
Rx chips.
Integrating Capacitor
The integrating capacitors (C2)
are required by both the Tx and
Rx to function properly. These
caps are used by the PLL for
frequency and phase lock and
directly set the stability and
lockup times. The designed value
of C2 is 0.1
μ
F, with a tolerance
of
±
10%. The internal charging
currents are scaled with the DIV0
and DIV1 settings such that the
same capacitor value works with
all four frequency bands. Larger
values of C2 improve jitter
performance, but extend the
lockup times.
Power Supply Bypassing and
Grounding
The G-LINK chip set has been
tested to work well with a single
Figure 19. Transmitter and Receiver Data Interface and Timing for Double Frame Mode (MDFSEL=0).
CONFIGTx
CAV*, DAV*
PLL
C00 - C19
STRBOUT
STRBIN
CONFIGRx
CAV*, DAV*, FF
LINKRDY,
ERROR
C00 - C19
STRBOUT
STAT0
STAT1
t
s
t
h
t
strb
CAV*, DAV*
STRBOUT
STRBIN
FLAG
CAV*, DAV*
FF, LINKRDY
ERROR
D00 - D19
STRBOUT
t
d1
t
s
= SETUP TIME
t
h
= HOLD TIME
t
strb
= STRBIN TO STRBOUT DELAY
t
mux
= 2:1 MULTIPLEXER DELAY
t
d1
= STRBOUT TO SYNCHRONOUS OUTPUTS DELAY
t
d2
= STRBOUT TO STATE MACHINE OUTPUTS DELAY
t
da
= STRBOUT TO RCLK DELAY
t
db
= RCLK TO C00-C39 OUTPUT DELAY
2:1
0
D00 - D19
C20 - C39
C20 - C39
D00 - D19
FLAG
FLAG
1/2 FRAME
PERIOD
1/2 FRAME
PERIOD
t
s
t
h
t
s
t
h
D00 - D19
t
s
t
h
C00 - C19
C20 - C39
C00 - C19
C20 - C39
t
mux
t
d2
STAT0
STAT1
FLAG
RCLK
C00 - C19
C20 - C39
C00 - C19
C20 - C39
t
da
t
da
t
db
t
db
RCLK
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