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參數(shù)資料
| 型號： | GS4900B |
| 廠商： | Gennum Corporation |
| 英文描述： | SD Clock and Timing Generator with GENLOCK |
| 中文描述： | 統(tǒng)計時鐘和定時發(fā)生器鎖相 |
| 文件頁數(shù)： | 82/95頁 |
| 文件大?。?/td> | 898K |
| 代理商： | GS4900B |
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GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
82 of 95
V_Start_2
5Eh
15
Reserved. Set this bit to zero when writing to 5Eh.
–
–
5Eh
14-0
The value programmed in this register indicates the start
line number of the leading edge of the
user-programmed V Sync signal USER2_V. For
interlaced output standards, this value corresponds to
the odd field line number.
NOTE: The value programmed in this register must be
less than the value programmed in V_Stop_2.
Reference:
Section 3.8.3 on page 59
R/W
0
V_Stop_2
5Fh
15
Reserved. Set this bit to zero when writing to 5Fh.
–
–
5Fh
14-0
The value programmed in this register indicates the end
line number of the trailing edge of the user-programmed
V Sync signal USER2_V. For interlaced output
standards, this value corresponds to the odd field line
number.
NOTE: The value programmed in this register must not
exceed the maximum number of lines per field of the
outgoing standard.
Reference:
Section 3.8.3 on page 59
R/W
0
Operator_Polarity_2
60h
15-4
Reserved. Set these bits to zero when writing to 60h.
–
–
60h
3
Polarity_2 - Use this bit to invert the polarity of the final
USER2 signal.
By default, the polarity of the user programmed signals
is active LOW. The polarity may be switched to active
HIGH by setting this bit LOW.
Reference:
Section 3.8.3 on page 59
R/W
1
60h
2
AND_2 - logical operator: USER2_H AND USER2_V
Set this bit HIGH to output a signal that is only active
when both USER2_H and USER2_V are active.
When this bit is HIGH, bit 1 and bit 0 of this register will
be ignored.
Reference:
Section 3.8.3 on page 59
R/W
0
60h
1
OR_2 - logical operator: USER2_H OR USER2_V
Set this bit HIGH to output a signal that is active
whenever USER2_H or USER2_V are active.
When this bit is HIGH bit 0 of this register will be
ignored.
Reference:
Section 3.8.3 on page 59
R/W
0
60h
0
XOR_2 - logical operator: USER2_H XOR USER2_V
Set this bit HIGH to output a signal with the following
attributes: Signal becomes active when either
USER2_H or USER2_V is active. Signal is inactive
when USER2_H and USER2_V are both active or both
inactive.
Reference:
Section 3.8.3 on page 59
R/W
0
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
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相關(guān)代理商/技術(shù)參數(shù) |
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| GS4900BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4901B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:SD Clock and Timing Generator with GENLOCK |
| GS4901B_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:SD Clock and Timing Generator with GENLOCK |
| GS4901BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4910B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
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