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GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
13 of 95
28, 29, 30
ACLK1
ACLK2
ACLK3
(GS4901B only)
–
Output
CLOCK SIGNAL OUTPUTS
Signal levels are LVCMOS/LVTTL compatible.
Audio output clock signals.
ACLK1, ACLK2, and ACLK3 present audio sample rate clock outputs to
the application layer.
By default, after system reset, the audio clock output pins of the device
provide clock signals as follows:
ACLK1 = 256fs
ACLK2 = 64fs
ACLK3 = fs, where fs is the fundamental sampling frequency.
The fundamental sampling frequency is selected using ASR_SEL[2:0].
Additional sampling frequencies may be programmed in the host
interface.
It is also possible to select different division ratios for each of the audio
clock outputs by programming designated registers in the host interface.
Clock outputs of 512fs, 384fs, 256fs, 192fs, 128fs, 64fs, fs and z bit are
selectable on a pin-by-pin basis.
NOTE: ACLK1-3 will have a 50% duty cycle, unless fs is selected as
96kHz and the host interface is configured such that one of the three
ACLK pins is set to output a clock signal at 192fs or 384fs. If this is the
case, then a 512fs clock will have a 33% duty cycle.
These signals will be high impedance when ASR_SEL[2:0] = 000b.
NC
(GS4900B only)
–
–
Do not connect.
32, 33, 34
ASR_SEL[2:0]
(GS4901B only)
Non
Synchronous
Input
CONTROL SIGNAL INPUTS
Signal levels are LVCMOS/LVTTL compatible.
Audio Sample Rate Select.
Used to select the fundamental sampling frequency, fs, of the audio clock
outputs. See
Table 3-7
.
When ASR_SEL[2:0] = 000b, audio clock generation will be disabled and
the ACLK1 to ACLK3 pins will be high impedance. In this case,
AUD_PLL_VDD (pin 14) may be connected to GND to minimize noise
and power consumption.
ANALOG_GND
(GS4900B only)
–
Power
Supply
Ground connection for the analog input block. Connect to GND.
35
TIMING_OUT_1
Synchronous
with PCLK1 ~
PCLK3
Output
TIMING SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Selectable timing output.
Selectable from: H sync; H blanking; V sync; V blanking; F sync; F
digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing
(GS4901B only); USER_1~4.
See
Section 1.5 on page 24
for signal descriptions.
NOTE: Default output is H Sync.
The current drive capability of this pin may be set high or low via
designated registers in the host interface. By default, the current drive
will be low.
This signal will be high impedance when VID_STD[5:0] = 00h.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS4900BCNE3 | SD Clock and Timing Generator with GENLOCK |
| GS4901B | SD Clock and Timing Generator with GENLOCK |
| GS4901BCNE3 | SD Clock and Timing Generator with GENLOCK |
| GS4910B | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4910BCNE3 | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS4900BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4901B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:SD Clock and Timing Generator with GENLOCK |
| GS4901B_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:SD Clock and Timing Generator with GENLOCK |
| GS4901BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4910B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
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