參數(shù)資料
型號: GS4900B
廠商: Gennum Corporation
英文描述: SD Clock and Timing Generator with GENLOCK
中文描述: 統(tǒng)計時鐘和定時發(fā)生器鎖相
文件頁數(shù): 19/95頁
文件大?。?/td> 898K
代理商: GS4900B
GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
19 of 95
Figure 1-1: XTAL1 and XTAL2 Reference Circuits
64
GENLOCK
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Selects Genlock mode or Free Run mode.
When this pin is set LOW and the device has successfully genlocked the
output to the input reference, the device will enter Genlock mode. The
video clock and timing outputs will be frequency and phase locked to the
detected reference signal.
When this pin is set HIGH, the video clock and the reference-timing
generator will free-run.
By default, the GS4901B’s audio clocks will be genlocked to the output
video clock regardless of the setting of this pin.
NOTE: The user must apply a reference to the input of the device prior to
setting GENLOCK = LOW. If the GENLOCK pin is set LOW and no
reference signal is present, the generated clock and timing outputs of the
device may correspond to the internal default settings of the chip until a
reference is applied.
Ground Pad
Ground pad on bottom of package must be soldered to main ground
plane of PCB.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
X1
38pF
X2
24pF
1M
6
7
X1
X2
6
7
NC
external
clock
External Crystal Connection
External Clock Source Connection
Notes:
1. Capacitor values listed represent the total capacitance,
including discrete capacitance and parasitic board capacitance.
2. X1 serves as an input, which may alternatively accept a 27MHz clock
source. To accomodate this, mismatched capacitor values are recommended.
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