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參數(shù)資料
| 型號： | GS4900B |
| 廠商： | Gennum Corporation |
| 英文描述： | SD Clock and Timing Generator with GENLOCK |
| 中文描述： | 統(tǒng)計時鐘和定時發(fā)生器鎖相 |
| 文件頁數(shù)： | 52/95頁 |
| 文件大?。?/td> | 898K |
| 代理商： | GS4900B |
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GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
52 of 95
3.7 Clock Synthesis
The clock synthesis circuit generates the video clocks based on the VID_STD[5:0]
pins and host register settings. In the GS4901B, the clock synthesis circuit also
generates the audio clock signals based on the ASR_SEL[2:0] pins and host
register settings.
The generated video and audio clocks may be further divided and are presented to
the application layer via pins PCLK1-PCLK3 and ACLK1-ACLK3 respectively.
3.7.1 Video Clock Synthesis
The video clock generator is referenced to an internal crystal oscillator and is
responsible for generating the PCLK output signals.
The crystal oscillator requires an external 27MHz crystal connected to pins X1 and
X2, or can be driven at LVTTL levels from an external 27MHz source connected to
X1. These two configurations are shown in
Figure 1-1
.
Four different video sample clock rates may be selected using the VID_STD[5:0]
pins of the device.
Section 1.4 on page 20
lists the video formats available using
the VID_STD[5:0] pins.
If desired, the external VID_STD[5:0] pins may be ignored by setting bit 1 of the
Video_Control register, and the video standard may instead be selected via the
VID_STD[5:0] register of the host interface (see
Section 3.10.3 on page 66
).
Although the external VID_STD[5:0] pins will be ignored, they should not be left
floating.
Once the video clock has been generated, it will be presented to the application
layer via the PCLK1 to PCLK3 pins. By default, each of the 3 video clock outputs
will produce the generated fundamental clock frequency. However, it is possible to
select other rates for each PCLK output by programming the PCLK_Phase/Divide
registers beginning at address 2Ch of the host interface (see
Section 3.10.3 on
page 66
).
Each PCLK output may be individually programmed to provide one of the following:
PCLK fundamental frequency
Fundamental frequency /2
Fundamental frequency /4
When all six VID_STD[5:0] pins are set LOW, the video clocks will be disabled.
PCLK1 and PCLK2 will go LOW and PCLK3/PCLK3 will be high impedance.
NOTE: If the PCLK divider bits of registers 2Ch - 2Eh are set to enable a divide by
2 or divide by 4, the resultant divided clock will align with the falling edge of the
output H Sync timing signal either on its rising or falling edge.
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| GS4900BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4901B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:SD Clock and Timing Generator with GENLOCK |
| GS4901B_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:SD Clock and Timing Generator with GENLOCK |
| GS4901BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4910B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
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