參數(shù)資料
型號： GS4900B
廠商： Gennum Corporation
英文描述： SD Clock and Timing Generator with GENLOCK
中文描述： 統(tǒng)計(jì)時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁數(shù)： 61/95頁
文件大?。?/td> 898K
代理商： GS4900B
GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
61 of 95
3.8.4 TIMING_OUT Pins
The horizontal, vertical, and frame based timing output signals for the selected
video format are available to the application layer via the TIMING_OUT_1 to
TIMING_OUT_8 pins.
Programmable Crosspoint Switch
Each TIMING_OUT pin outputs a default signal as shown in
Table 1-3
.
Alternatively, a crosspoint switch may be programmed via the eight Output_Select
registers of the host interface, allowing the user to select which output signal is
directed to each TIMING_OUT pin (see
Section 3.10.3 on page 66
). Any signal
may be sent to more than one pin if desired.
Table 3-11
outlines the encoding scheme of the eight Output_Select registers,
which begin at address 43h of the host interface.
3.8.4.1 Selectable Current Drive and Polarity
The current-drive of each timing output pin is also selectable via the Output_Select
registers. The current drive of each TIMING_OUT pin is low by default. However,
it may be set high to accommodate certain applications.
Additionally, the Polarity register of the host interface may be programmed to select
the polarity of each timing output signal.
Table 3-11: Crosspoint Select
Output_Select_n Bit Settings
Output Signal
0000
High Impedance
0001
H Sync
0010
H Blanking
0011
V Sync
0100
V Blanking
0101
F Sync
0110
F Digital
0111
10FID
1000
DE
1001
Reserved
1010
AFS*
1011
USER_1
1100
USER_2
1101
USER_3
1110
USER_4
1111
Reserved
*AFS is only available on the GS4901B. The bit setting 1010b will be ignored by the GS4900B.
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