參數(shù)資料
型號(hào)： GS4900B
廠商： Gennum Corporation
英文描述： SD Clock and Timing Generator with GENLOCK
中文描述： 統(tǒng)計(jì)時(shí)鐘和定時(shí)發(fā)生器鎖相
文件頁(yè)數(shù)： 76/95頁(yè)
文件大小： 898K
代理商： GS4900B
GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
76 of 95
Audio_Cap_Genlock
(GS4901B only)
39h
15-6
Reserved. Set these bits to zero when writing to 39h.
–
–
39h
5-0
Control signal to adjust loop bandwidth of audio genlock
block.
The value programmed in this register must be between
10 and Audio_Res_Genlock - 21.
The default value of this register will depend on the
fundamental sampling frequency selected.
Reference:
Section 3.6.2 on page 48
R/W
–
Audio_Res_Genlock
(GS4901B only)
3Ah
15-6
Reserved. Set these bits to zero when writing to 3Ah.
–
–
3Ah
5-0
Control signal to adjust loop bandwidth of audio genlock
block.
The value programmed in this register must be between
32 and 42.
The default value of this register will depend on the
fundamental sampling frequency selected.
Reference:
Section 3.6.2 on page 48
R/W
–
RSVD
3Bh-3Eh
–
Reserved
–
–
ACLK1_fs_Multiple
(GS4901B only)
3Fh
15-3
Reserved. Set these bits to zero when writing to 3Fh.
–
–
3Fh
2-0
The user may set this register to select the desired
frequency of the audio clock on ACLK1 (a multiple of the
fundamental sampling rate, fs). The audio clock
frequency may be set as: 512fs, 384fs, 256fs, 192fs,
128fs, 64fs, fs, or z-bit. See
Table 3-8
for more details.
NOTE: To output a frequency of 348fs or 192fs, bit 5 of
register 31h must also be set HIGH.
Reference:
Section 3.7.2 on page 53
R/W
0
ACLK2_fs_Multiple
(GS4901B only)
40h
15-3
Reserved. Set these bits to zero when writing to 40h.
–
–
40h
2-0
The user may set this register to select the desired
frequency of the audio clock on ACLK2 (a multiple of the
fundamental sampling rate, fs). The audio clock
frequency may be set as: 512fs, 384fs, 256fs, 192fs,
128fs, 64fs, fs, or z-bit. See
Table 3-8
for more details.
NOTE: To output a frequency of 348fs or 192fs, bit 5 of
register 31h must also be set HIGH.
Reference:
Section 3.7.2 on page 53
R/W
0
ACLK3_fs_Multiple
(GS4901B only)
41h
15-3
Reserved. Set these bits to zero when writing to 41h.
–
–
41h
2-0
The user may set this register to select the desired
frequency of the audio clock on ACLK3 (a multiple of the
fundamental sampling rate, fs). The audio clock
frequency may be set as: 512fs, 384fs, 256fs, 192fs,
128fs, 64fs, fs, or z-bit. See
Table 3-8
for more details.
NOTE: To output a frequency of 348fs or 192fs, bit 5 of
register 31h must also be set HIGH.
Reference:
Section 3.7.2 on page 53
R/W
0
RSVD
42h
–
Reserved.
–
–
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
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