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參數(shù)資料
| 型號： | GS4900B |
| 廠商： | Gennum Corporation |
| 英文描述： | SD Clock and Timing Generator with GENLOCK |
| 中文描述： | 統(tǒng)計時鐘和定時發(fā)生器鎖相 |
| 文件頁數(shù)： | 80/95頁 |
| 文件大?。?/td> | 898K |
| 代理商： | GS4900B |
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GS4901B/GS4900B Preliminary Data Sheet
37703 - 0
April 2006
80 of 95
56h
4
F_Sync - set this bit HIGH to invert the polarity of the F
Sync timing output signal.
By default, the F Sync signal will be HIGH for the entire
period of field 1.
Reference:
Table 1-3
R/W
0
56h
3
V_Blanking - set this bit HIGH to invert the polarity of the
V Blanking timing output signal.
By default, the V Blanking signal will be LOW for the
portion of the field/frame containing valid video data.
Reference:
Table 1-3
R/W
0
56h
2
V_Sync - set this bit HIGH to invert the polarity of the V
Sync timing output signal.
By default, the V Sync signal is active LOW.
Reference:
Table 1-3
R/W
0
56h
1
H_Blanking - set this bit HIGH to invert the polarity of
the H Blanking timing output signal.
By default, the H Blanking signal will be LOW for the
portion of the video line containing valid video samples.
Reference:
Table 1-3
R/W
0
56h
0
H_Sync - set this bit HIGH to invert the polarity of the H
Sync timing output signal.
By default, the H Sync signal is active LOW.
Reference:
Table 1-3
R/W
0
H_Start_1
57h
15-0
The value programmed in this register indicates the
pixel start point for the leading edge of the
user-programmed H Sync signal USER1_H.
NOTE: The value programmed in this register must be
less than the value programmed in H_Stop_1.
Reference:
Section 3.8.3 on page 59
R/W
0
H_Stop_1
58h
15-0
The value programmed in this register indicates the
pixel end point for the trailing edge of the
user-programmed H Sync signal USER1_H.
NOTE: The value programmed in this register must not
exceed the maximum number of clock periods per line
of the outgoing standard.
Reference:
Section 3.8.3 on page 59
R/W
0
V_Start_1
59h
15
Reserved. Set this bit to zero when writing to 59h.
–
–
59h
14-0
The value programmed in this register indicates the start
line number of the leading edge of the
user-programmed V Sync signal USER1_V. For
interlaced output standards, this value corresponds to
the odd field number.
NOTE: The value programmed in this register must be
less than the value programmed in V_Stop_1.
Reference:
Section 3.8.3 on page 59
R/W
0
Table 3-13: Configuration and Status Registers (Continued)
Register Name
Address
Bit
Description
R/W
Default
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| GS4900BCNE3 | SD Clock and Timing Generator with GENLOCK |
| GS4901B | SD Clock and Timing Generator with GENLOCK |
| GS4901BCNE3 | SD Clock and Timing Generator with GENLOCK |
| GS4910B | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
| GS4910BCNE3 | HD/SD/Graphics Clock and Timing Generator with GENLOCK |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS4900BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4901B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:SD Clock and Timing Generator with GENLOCK |
| GS4901B_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:SD Clock and Timing Generator with GENLOCK |
| GS4901BCNE3 | 功能描述:IC RE-TIMER RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| GS4910B | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD/SD/Graphics Clock and Timing Generator with GENLOCK |
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