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參數(shù)資料
| 型號(hào)： | GL9711 |
| 廠商： | Genesys Logic, Inc. |
| 英文描述： | PCI ExpressTM PIPE x1 PHY |
| 中文描述： | 的PCI ExpressTM管x1物理層 |
| 文件頁數(shù)： | 35/42頁 |
| 文件大?。?/td> | 423K |
| 代理商： | GL9711 |
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GL9711 PCI Express
TM
PIPE x1 PHY
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 35
7.4 Power Consumption
l
Power Consumption
Table 7.4 - Power Consumption of Each Power State in Different Operation Mode
Current at 2.5V
(mA)
Current at
Analogue 1.8V
(mA)
Current at
Digital 1.8V
(mA)
Operation
Condition
Power
State
Operation Mode
Power
Consumption
(mW)
59
90
57
All on
P0
16-bit @125MHz
PCLK
412.1
12
71
49
PLL on
TX idle
RX on
P0s
16-bit @125MHz
PCLK
246
12
64
38
PLL on
TX idle
RX idle
P1
16-bit @125MHz
PCLK
213.6
6
36
6
PLL off
TX idle
RX idle
P2
16-bit @3.13MHz
PCLK
90.6
7.5 Differential Transmitter and Receiver Serial Output
l
Transmitter Serial Output
Table 7.5
–
Transmitter Serial Output
Symbol
Parameter
Min
Typ
Max
Unit
UI
Unit interval
399.88
400
400.12
ps
V
TX-DIFFp-p
Differential peak to peak output voltage
De-emphasized
differential
voltage (Ratio)
Minimum TX eye width
Maximum time between the jitter
median and maximum deviation from
the median
0.8
-
1.2
UI
V
TX-DE-RATIO
output
-3.0
-3.5
-4.0
dB
T
TX-EYE
0.7
-
-
UI
T
TX-EYE-MEDIAN-to-MAX-JITTER
-
-
0.15
UI
T
TX-RISE
,
T
TX-FALL
D+/D- TX output rise/fall time
0.125
-
-
UI
V
TX-CM-ACp
RMS AC peak common mode output
voltage
-
-
20
mA
V
TX-CM-DC-ACTIVE-IDLE-DELTA
Absolute delta of DC common mode
voltage during L0 and electrical idle
Absolute delta of DC common mode
voltage between D+ and D-
V
TX-IDLE-DIFFp
Electrical idle differential peak output
0
-
100
mA
V
TX-CM-DC-LINE-DELTA
0
-
25
mA
0
-
20
mA
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