參數(shù)資料
型號： GL9711
廠商： Genesys Logic, Inc.
英文描述： PCI ExpressTM PIPE x1 PHY
中文描述： 的PCI ExpressTM管x1物理層
文件頁數(shù)： 29/42頁
文件大小： 423K
代理商： GL9711
GL9711 PCI Express
TM
PIPE x1 PHY
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 29
CHAPTER 6 FUNCTION DESCRIPTION
6.1 Clock and Reset
The clock source of the GL9711 comes externally from either the 100 MHz differential clock pair or the 25MHz
crystal, which is selectable by pin SCC. The GL9711 uses the clock source with its PLL to generate the 2.5 GHz
bit rate for transmitting and receiving.
The GL9711 also drives a clock output for the synchronization of MAC interface. Since the MAC interface can
be configured to 8-bit, 16-bit and 10-bit mode, the clock, PCLK, runs at 250 MHz for 8-bit mode and 125 MHz
for 16-bit mode. The MAC should use the rising edge of the clock to send and receive parallel data.
To initialize the GL9711, the MAC should assert the reset of the GL9711 to low. While the reset is asserted, the
MAC should also make TXDET/LPBK deasserted, TXIDLE asserted, TXCMP deasserted, RXPLR deasserted
and PD[1:0] = P1. When the GL9711 senses its reset asserted, it will drive its PHYSTS high immediately. After
the reset deasserted, the GL9711 requires typically 16.7us for internal PLL stable and then transitions its
PHYSTS to low. When MAC deasserts the reset, it should monitor the state of PHYSTS to make sure the
GL9711 is ready for normal operation.
6.2 Receiver Detection
The receiver detection can only be performed while the GL9711 is in P1 state. To instruct the GL9711 to enter a
receiver detection sequence, the MAC asserts TXDET/LPBK and hold it asserted until the GL9711 asserts
PHYSTS for response. While finishing the receiver detection, the GL9711 will assert PHYSTS and present a
appropriate value to RXSTS[2:0] to signal a detection completion. When the MAC detects PHYSTS asserted, it
knows the detection result from RXSTS[2:0] and can deassert TXDET/LPBK.
6.3 Beacon Transmitting and Detection
Beacon transmitting is required for the GL9711 in P2 state to wake up the receiver in the other side of the link.
When the GL9711 is in P2 state, the MAC can deassert TXIDLE to instruct the GL9711 to repeatedly transmit a
beacon.
For the beacon receiving side, if the GL9711 receives a beacon, it will transition RXIDLE to low to indicate an
exit from electrical idle. When the GL9711 is in P2 state and MAC senses the RXIDLE transitioned from high to
low, it knows a beacon has been detected.
6.4 Receiver Status Report
l
Add and Remove a SKP
The GL9711 implements an elastic buffer to compensate the clock rate difference between the recovery clock
and its transmit clock. While receiving a SKP ordered-set, compliant to PCI Express Base specification
REV. 1.0a, the GL9711 can insert or remove one SKP symbol in the SKP ordered-set to avoid the buffer
overrun or underrun. Whenever adding or removing a SKP symbol, the GL9711 will signal PHYSTS and
corresponding RXSTS[2:0] to MAC.
SKP Ordered-Set Received
Add a SKP
Remove a SKP
RXSTS Code
001b
010b
Receiver Detected
l
Detected Result
Receiver not present
Receiver present
RXSTS code
000b
011b
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