參數(shù)資料
型號(hào)： GL9711
廠商： Genesys Logic, Inc.
英文描述： PCI ExpressTM PIPE x1 PHY
中文描述： 的PCI ExpressTM管x1物理層
文件頁(yè)數(shù)： 19/42頁(yè)
文件大?。?/td> 423K
代理商： GL9711
GL9711 PCI Express
TM
PIPE x1 PHY
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 19
CHAPTER 4 REGISTERS
There are some registers built-in the GL9711 for test purpose. These registers can be accessed through a serial
bus interface using pin TESTC and TESTD. Registers at Offset 05h ~ 0Bh are for internal test only. Please be
careful to leave them as default values.
4.1 Registers Base Address
Table 4.1 - Base Address for Registers
Mnemonic
Offset
Description
Default
REVID
00h
Revision ID and Auto-calibration Result Register
8
’
bxxxx1xxx
XCVROPT
01h
Transceiver Option Register
8
’
hE9
LPBKTEST
02h
BIST and Beacon/Test Data Pattern Register, Part 1
8
’
h00
BCNPAT2
03h
Beacon/Test Data Pattern Register, Part 2
8
’
h03
BCNPAT3
04h
Beacon/Test Data Pattern Register, Part 3
8
’
hFF
-
05h
For internal test only
-
-
06h
For internal test only
-
-
-
-
-
-
-
07h
For internal test only
-
08h
For internal test only
-
09h
For internal test only
-
0Ah
For internal test only
-
0Bh
For internal test only
BT
0Ch
Buffer Test Register
8
’
h00
8
’
h00
SLCDT
0Dh
Serial Loopback and Comma Detect Test Register
Notation:
R/W
R/O
W/O
R/W1C
R/W/C
Read / Write
Read Only
Write Only
Read / Write
“
1
”
to Clear
Read / Write and hardware automatic Clear
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