
GL9711 PCI Express
TM
PIPE x1 PHY
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 3
Revision History
Revision
Date
Description
0.95
7/11/2005
Preliminary release
1. Modify Table3.1
–
Ball Out, p.11
2. Modify
“
PIPE Interface
”
and
“
Other Signals
”
, Table3.4
–
Pin
Descriptions, p.15~p.17
3. Modify Ch4.2 Registers Descriptions, p.19
4. Modify Ch6.10 Operation Mode and Multi-Functional Pins, p.28
5. Modify Table6.1-Pin Functions, p.28~p.30
6. Modify Table8.1~8.5, p.36~p.37
09/20/2005 Modify Package Dimension,Ch9 , p.40
1. Add
“
Bottom View
”
, Figures.3.1, p.10
2. Update Table3.4, p.15~p.18
3. Update Table3.5, p.18
4. Modify the default value of REG0 and REG1, Table4.1, p.19
5. Modify Ch4.2 Registers Descriptions for REG0 and REG1, p.20
6. Add Ch 4.3, p.22~p.25
7. Update Table 7.5 for power consumption, p.35
8. Change TXDx to RXDx, Figure 8.4, p.39
9. The minimum and maximum value of T
CYCLE,
Table8.2 and Table 8.5,
p.40
1. Update Table 7.8 for temperature ranges (p.37)
2. Update Table 8.1~8.4 for output delay of RX bus (p.39~p.40)
1. Modify the description of OSC25MI and OSC25MO signals, Table
3.4, p.15
2. Swap the Pin Out of OSC25MI and OSC25MO in Table 3.1~Table
3.4.
3. Update Table 7.1 for deleting I
DD1-X4
, I
DD2-X4
, I
DD3-X4
, I
DD1-X2
, I
DD2-X2
,
and I
DD3-X2
six items, p.34
4. Update Table 7.8 for deleting the I
SUPPLY-1.8
item and adding
θ
JA
,
Ψ
JT
and
θ
JC
three items, p.37
Divide Table 7.8 into Table 7.8(Temperature Range) and Table
7.9(Thermal Characteristics), p.37
1. Update Table 3.5 for the parameter of buffer I/O, p.18
2. Remove Table 7.2, p.34
3. Update Fig. 8.1, 8.2 and Table 8.1~8.5 for PIPE input and output
timing characteristic, p.38~p.40
0.96
7/27/2005
0.97
0.98
11/15/2005
1.00
12/15/2005
1.01
04/13/2006
1.02
04/26/2006
1.10
07/04/2006