參數(shù)資料
型號(hào): GL9711
廠商: Genesys Logic, Inc.
英文描述: PCI ExpressTM PIPE x1 PHY
中文描述: 的PCI ExpressTM管x1物理層
文件頁數(shù): 23/42頁
文件大?。?/td> 423K
代理商: GL9711
GL9711 PCI Express
TM
PIPE x1 PHY
2000-2006 Genesys Logic Inc. - All rights reserved.
Page 23
SMBus uses fixed voltage levels to define the logic
ZERO
and logic
ONE
on the bus respectively. The data
on SMBDAT must be stable during the
HIGH
period of the clock. Data can change state only when SMBCLK
is low. Fig. 4.2 illustrates the relationships.
Figure 4.2
Data Validity
Two unique bus situations define a message START and STOP condition.
1. A HIGH to Low transition of the SMBDAT line while SMBCLK is HIGH indicates a message START
condition.
2. A LOW to HIGH transition of the SMBDAT line while SMBCLK is HIGH defines a message STOP
condition.
Figure 4.3
START and STOP Condition
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