參數(shù)資料
型號(hào)： FX919A
英文描述： 4-Level FSK Packet Data Modem
中文描述： 四級(jí)別FSK信號(hào)分組數(shù)據(jù)調(diào)制解調(diào)器
文件頁(yè)數(shù)： 7/44頁(yè)
文件大?。?/td> 1537K
代理商： FX919A
4-Level FSK Modem Data Pump
FX919A
1996 Consumer Microcircuits Limited
7
D/919A/4
1.5
General Description
1.5.1
Description of Blocks
Data Bus Buffers
Eight bidirectional 3-state logic level buffers between the modem's internal registers and the host μC's data bus
lines.
Address and R/W Decode
This block controls the transfer of data bytes between the μC and the modem's internal registers, according to
the state of the Write and Read Enable inputs (WRN and RDN), the Chip Select input (CSN) and the Register
Address inputs A0 and A1.
The Data Bus Buffers, Address and R/W Decode blocks provide a byte-wide parallel μC interface, which can
be memory-mapped, as shown in Figure 3.
Figure 3 Typical Modem μC Connections
Status and Data Quality Registers
Eight-bit registers which the μC can read to determine the status of the modem and the received data quality.
Command, Mode and Control Registers
The values written by the μC to these 8-bit registers control the operation of the modem.
Data Buffer
A 12-byte buffer used to hold receive or transmit data to or from the μC.
CRC Generator/Checker
A circuit which generates (in transmit mode) or checks (in receive mode) the Cyclic Redundancy Checksum
bits, which may be included in transmitted data blocks so that the receive modem can detect transmission
errors.
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