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參數(shù)資料
| 型號(hào)： | FX919A |
| 英文描述： | 4-Level FSK Packet Data Modem |
| 中文描述： | 四級(jí)別FSK信號(hào)分組數(shù)據(jù)調(diào)制解調(diào)器 |
| 文件頁數(shù)： | 14/44頁 |
| 文件大小： | 1537K |
| 代理商： | FX919A |
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4-Level FSK Modem Data Pump
FX919A
1996 Consumer Microcircuits Limited
14
D/919A/4
1.5.5.2
Command Register
Writing to this register tells the modem to perform a specific action or actions, depending on the setting of the
TASK, AQLEV and AQSC bits.
When it has no action to perform, the modem will be in an 'idle' state. If the modem is in transmit mode the input
to the Tx RRC filter will be connected to V
BIAS
. In receive mode the modem will continue to measure the
received data quality and extract symbols from the received signal, supplying them to the de-interleave buffer,
but will otherwise ignore the received data.
Command Register B7: AQSC - Acquire Symbol Clock
This bit has no effect in transmit mode.
In receive mode, whenever a byte with the AQSC bit set to '1' is written to the Command Register, and TASK is
not set to RESET, it initiates an automatic sequence designed to achieve symbol timing synchronisation with
the received signal as quickly as possible. This involves setting the Phase Locked Loop of the received bit
timing extraction circuits to its widest bandwidth, then gradually reducing the bandwidth as timing
synchronisation is achieved, until it reaches the 'normal' value set by the PLLBW bits of the Control Register.
Setting this bit to '0' (or changing it from '1' to '0') has no effect, however note that the acquisition sequence will
be re-started every time that a byte written to the Command Register has the AQSC bit set to '1'.
The use of the symbol clock acquisition sequence is described in section 1.6.3.
Command Register B6: AQLEV - Acquire Receive Signal Levels
This bit has no effect in transmit mode.
In receive mode, whenever a byte with the AQLEV bit set to '1' is written to the Command Register and TASK
is not set to RESET, it initiates an automatic sequence designed to measure the amplitude and dc offset of the
received signal as rapidly as possible. This sequence involves setting the measurement circuits to respond
quickly at first, then gradually increasing their response time, hence improving the measurement accuracy, until
the 'normal' value set by the LEVRES bits of the Control Register is reached.
Setting this bit to '0' (or changing it from '1' to '0') has no effect, however note that the acquisition sequence will
be re-started every time that a byte written to the Command Register has the AQLEV bit set to '1'.
The use of the level measurement acquisition sequence (AQLEV) is described in section 1.6.3.
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