參數(shù)資料
型號： FX919A
英文描述： 4-Level FSK Packet Data Modem
中文描述： 四級別FSK信號分組數(shù)據(jù)調(diào)制解調(diào)器
文件頁數(shù)： 26/44頁
文件大?。?/td> 1537K
代理商： FX919A
4-Level FSK Modem Data Pump
FX919A
1996 Consumer Microcircuits Limited
26
D/919A/4
Status Register B7: IRQ - Interrupt Request
This bit is set to '1' by:
The Status Register BFREE bit going from '0' to '1', unless this is caused by a RESET task or by a
change to the Mode Register TXRXN or PSAVE bits.
or
The Status Register IBEMPTY bit going from '0' to '1', unless this is caused by a RESET task or by
changing the Mode Register TXRXN or PSAVE bits.
or
The Status Register DIBOVF bit going from '0' to '1'.
The IRQ bit is cleared to '0' immediately after a read of the Status Register.
If the IRQNEN bit of the Mode Register is '1', then the chip IRQN output will be pulled low (to VSS) whenever
the IRQ bit is set to '1', and will go high impedance when the Status Register is read.
Status Register B6: BFREE - Data Block Buffer Free
This bit reflects the availability of the Data Block Buffer and is cleared to '0' whenever a task other than NULL or
RESET is written to the Command Register.
In transmit mode, the BFREE bit will be set to '1' (also setting the Status Register IRQ bit to '1') by the modem
when the modem is ready for the μC to write new data to the Data Block Buffer and the next task to the
Command Register.
In receive mode, the BFREE bit is set to '1' (also setting the Status Register IRQ bit to '1') by the modem when
it has completed a task and any data associated with that task has been placed into the Data Block Buffer. The
μC may then read that data and write the next task to the Command Register.
The BFREE bit is also set to '1' - but without setting the IRQ bit - by a RESET task or when the Mode Register
TXRXN or PSAVE bits are changed.
Status Register B5: IBEMPTY - Interleave Buffer Empty
In transmit mode, this bit will be set to '1' - also setting the IRQ bit - when less than two symbols remain in the
Interleave Buffer. Any transmit task written to the modem after this bit goes to '1' will be too late to avoid a gap
in the transmit output signal.
The bit is also set to '1' by a RESET task or by a change of the Mode Register TXRXN or PSAVE bits, but in
these cases the IRQ bit will not be set.
The bit is cleared to '0' within one symbol time after a task other than NULL or RESET is written to the
Command Register.
Note: When the modem is in transmit mode and the Interleave Buffer is empty, a mid level (half-way between
'+1' and '-1') signal will be sent to the RRC filter.
In receive mode this bit will be '0'.
Status Register B4: DIBOVF - De-Interleave Buffer Overflow
In receive mode this bit will be set to '1' - also setting the IRQ bit - when a RHB, RILB or R4S task is written to
the Command Register too late to allow continuous reception.
The bit is cleared to '0' immediately after reading the Status Register, by writing a RESET task to the Command
Register or by changing the TXRXN or PSAVE bits of the Mode Register.
In transmit mode this bit will be '0'.
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