參數(shù)資料
型號(hào)： FX919A
英文描述： 4-Level FSK Packet Data Modem
中文描述： 四級(jí)別FSK信號(hào)分組數(shù)據(jù)調(diào)制解調(diào)器
文件頁(yè)數(shù)： 15/44頁(yè)
文件大小： 1537K
代理商： FX919A
4-Level FSK Modem Data Pump
FX919A
1996 Consumer Microcircuits Limited
15
D/919A/4
Command Register B5: CRC
This bit allows the user to select between two different forms of the CRC1 and CRC2 checksums. When this
bit is set to '0' the CRC generators are initialised to 'all ones' as for CCITT X25 CRC calculations. When this bit
is set to '1' the CRC generators are initialised to 'all zeros'. Setting this bit to '0' gives compatibility with the
older 'non-A' version of the FX919, other systems may set this bit as required.
Command Register B4, B3
These bits should always be set to '0'.
Command Register B2, B1, B0: TASK
Operations such as transmitting or receiving a data block are treated by the modem as 'tasks' and are initiated
when the μC writes a byte to the Command Register with the TASK bits set to anything other than the 'NULL'
code.
The μC should not write a task (other than NULL or RESET) to the Command Register or write to or read from
the Data Buffer when the BFREE (Buffer Free) bit of the Status Register is '0'.
Different tasks apply in receive and transmit modes.
When the modem is in transmit mode, all tasks other than NULL or RESET instruct the modem to transmit data
from the Data Buffer, formatting it as required. The μC should therefore wait until the BFREE (Buffer Free) bit of
the Status Register is '1', before writing the data to the Data Block Buffer, then it should write the desired task
to the Command Register. If more than 1 byte needs to be written to the Data Block Buffer, byte number 0 of
the block should be written first.
Once the byte containing the desired task has been written to the Command Register, the modem will:
Set the BFREE (Buffer Free) bit of the Status Register to '0'.
Take the data from the Data Block Buffer as quickly as it can - transferring it to the Interleave Buffer for
eventual transmission. This operation will start immediately if the modem is 'idle' (i.e. not transmitting
data from a previous task), otherwise it will be delayed until there is sufficient room in the Interleave
Buffer.
Once all of the data has been transferred from the Data Block Buffer the modem will set the BFREE
and IRQ bits of the Status Register to '1', (causing the chip IRQN output to go low if the IRQNEN bit of
the Mode Register has been set to '1') to tell the μC that it may write new data and the next task to the
modem.
This lets the μC write a task and the associated data to the modem while the modem is still transmitting the
data from the previous task.
TXOP signal
from task 1
from task 2
Task 1
Task 2
Data from μC to Block Buffer
Task from μC to Command Register
IRQ bit of Status Register
BFREE bit of Status Register
IRQN o/p (IRQNEN = '1')
Figure 8 Transmit Task Overlapping
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