參數(shù)資料
型號(hào)： FX919A
英文描述： 4-Level FSK Packet Data Modem
中文描述： 四級(jí)別FSK信號(hào)分組數(shù)據(jù)調(diào)制解調(diào)器
文件頁(yè)數(shù)： 23/44頁(yè)
文件大?。?/td> 1537K
代理商： FX919A
4-Level FSK Modem Data Pump
FX919A
1996 Consumer Microcircuits Limited
23
D/919A/4
Control Register B5, B4: FSTOL - Frame Sync Tolerance
These two bits have no effect in transmit mode. In receive mode, they define the maximum number of
mismatches which will be allowed during a search for the Frame Sync pattern:
B5
0
0
1
1
B4
0
1
0
1
Mismatches allowed
0
2
4
6
Note: A single 'mismatch' is defined as the difference between two adjacent symbol levels, thus if the symbol
'+1' were expected, then received symbol values of '+3' and '-1' would count as 1 mismatch, a received symbol
value of '-3' would count as 2 mismatches. A setting of '4 mismatches' is recommended for normal use.
Control Register B3, B2: LEVRES - Level Measurement Modes
These two bits have no effect in transmit mode. In receive mode they set the 'normal' operating mode of the
received signal amplitude and dc offset measuring circuits (the automatic sequencing of an AQLEV command
may temporarily override the 'normal' setting).
B3
0
0
1
1
B2
Mode
0
Hold
1
Slow Peak Detect
0
Lossy Peak Detect
1
Clamp
In normal use the LEVRES bits should be set to 'Slow Peak Detect', the other modes are intended for special
test purposes or are invoked automatically during an AQLEV sequence.
In the 'Slow' and 'Lossy' Peak Detect modes the positive and negative excursions of the received signal (after
filtering) are measured by peak rectifiers driving the DOC1 and DOC2 capacitors, to establish the amplitude of
the signal and any dc offset wrt VBIAS . The peak rectifiers are disabled in 'Hold' mode.
In 'Clamp' mode the DOC1 and DOC2 pins are connected directly to the output of the circuit that normally
drives the peak detectors.
Control Register B1, B0: PLLBW - Phase-Locked Loop Modes
These two bits have no effect in transmit mode. In receive mode, they set the 'normal' bandwidth of the Rx
clock extraction Phase Locked Loop circuit. This setting will be temporarily overridden by the automatic
sequencing of an AQSC command.
B1
0
0
1
1
B0 PLL Mode
0
Hold
1
Narrow Bandwidth
0
Medium Bandwidth
1
Wide Bandwidth
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