參數(shù)資料
型號(hào)： FUSB2805MLX
廠商： Fairchild Semiconductor
文件頁數(shù)： 7/49頁
文件大?。?/td> 0K
描述： TXRX USB2.0 HS OTG ULPI 32MLP
標(biāo)準(zhǔn)包裝： 1
系列： *
其它名稱： FUSB2805MLXFSDKR
2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB2805 Rev. 1.0.3
15
F
USB2
8
0
5
—
USB2
.0
High
-S
pee
d
OTG
Tra
nsc
e
iv
e
rw
ith
UL
P
I
Inter
fac
e
VCC
V
IO
Chip_Select_N
Regulator Powerup
Internal PORB
CLKIN
Clock (output)
D[7:0]
NXT
Reset Command
Clock Start
Internal clock stable
Internal reset
RXCMD
Update
Powerup
Bus Idle
DIR
STP
TXCMD
DATA
t1 t2
t3
t4
t5
t6
t
PWRUP
t
startPLL
Figure 9. Power-up, Reset, and Bus Idle Sequence for ULPI Ready
Notes:
4.
With the CLKIN stable, the FUSB2805 drives a 60 MHz clock out from the CLOCK pin when DIR de-asserts.
This is shown as “CLOCK (output)” above.
5.
t1: VCC is applied to the FUSB2805.
6.
t3: Chip_Select_N transitions to active state (LOW). FUSB2805 internal regulator turns on and the ULPI pins
become active (may be driven HIGH or LOW), but should be ignored during the power-up time tPWRUP.
7.
t4: After the POR pulse (Power-On Reset), the ULPI pins are driven to a defined level. DIR is driven HIGH, then
the other ULPI pins are driven LOW.
8.
t5: The PLL stabilizes after the PLL startup time, tstartPLL. The CLOCK pin begins to output 60 MHz, the DIR pin
transitions LOW, and the link must drive STP and D[7:0] to LOW (idle). The link then initiates a reset command
to initialize the FUSB2805.
9.
t6: The power-up sequence is completed and the ULPI bus interface is ready for use.
VBUS Power and Over-Current Detection
Driving 5 V on VBUS – External Only
No
internal
charge
pump
is
supported
by
the
FUSB2805. The PSW pin supports an external
VBUS
supply and is an active HIGH (open source) signal used
to control external power management integrated
circuits, such as OTG support SMPS devices.
Over-Current Detection
Only external over-current detection is supported by the
FUSB2805. An over-current detection circuit is required
for host applications that supply more than 100 mA on
VBUS between voltages of 4.75 V to 5.25 V.
A digital signal from this external circuit must be
connected to the FAULT pin, which directly controls the
PSW pin (as shown in Figure 5). The polarity of the signal
input to this pin, which controls PSW, is selectable.
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