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參數(shù)資料
| 型號： | FUSB2805MLX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數(shù)： | 27/49頁 |
| 文件大?。?/td> | 0K |
| 描述： | TXRX USB2.0 HS OTG ULPI 32MLP |
| 標準包裝： | 1 |
| 系列： | * |
| 其它名稱： | FUSB2805MLXFSDKR |
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2008 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FUSB2805 Rev. 1.0.3
33
F
USB2
8
0
5
—
USB2
.0
High
-S
pee
d
OTG
Tra
nsc
e
iv
e
rw
ith
UL
P
I
Inter
fac
e
Serial Modes
3-pin serial modes as controlled in the INTF_CTRL
register via the 6-pin and 3-pin register bits.
Please refer to ULPI specification, section 3.10 for
details on the 3-pin and 6-pin serial mode functionality.
DATA[0]
Tx_Enable
DATA[1]
Tx_DAT/
RX_RCV
DATA[2]
Tx_SE0/
RX_SE0
DP
DM
TRANSMIT
SYNC
DATA
EOP
SYNC
DATA
EOP
RECEIVE
Figure 21.
3-Pin Serial Mode
– Transmit and Receive Example
DATA[0]
Tx_Enable
DATA[1]
Tx_DAT
DATA[2]
Tx_SE0
DP
DM
TRANSMIT
SYNC
DATA
EOP
SYNC
DATA
EOP
RECEIVE
DATA[5]
Rx_DM
DATA[6]
Rx_RCV
DATA[4]
Rx_DP
Figure 22.
6-Pin Serial Mode
– Transmit and Receive Example
Avoiding Contention on the ULPI Data Bus
Because the ULPI data bus is bi-directional, it is
necessary to avoid situations in which both the link and
FUSB2805 drive the data bus simultaneously.
The following points should be considered while
implementing the data bus drive control on the link.
After the power-up and clock stabilization, the default
states are:
FUSB2805 drives DIR=0.
Data bus is an INPUT to FUSB2805.
HOST/LINK ULPI data bus is OUTPUT (with all
data bus bits driven to 0).
When FUSB2805 wants to take control of data bus to
initiate a data transfer, it changes DIR value from 0 to 1.
At this point, HOST/LINK should disable its output pad
buffers. This needs to be as fast as possible, so LINK
should use a combinational path from DIR.
FUSB2805
does
not
enable
its
output
buffers
immediately, but delays the enabling buffers until the
next clock edge, avoiding bus contention.
When data transfer is no longer required by the
FUSB2805, it changes DIR from 1 to 0 and starts to turn
off its output drivers immediately. The HOST/LINK
senses the change of DIR from 1 to 0, but delays
enabling its output buffers for one CLOCK cycle,
thereby avoiding data bus contention.
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